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首页> 外文期刊>IEEE Transactions on Parallel and Distributed Systems >Exploring the Design Space of Self-Regulating Power-Aware On/Off Interconnection Networks
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Exploring the Design Space of Self-Regulating Power-Aware On/Off Interconnection Networks

机译：探索自调节电源感知的开/关互连网络的设计空间

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摘要

With power consumption becoming increasingly critical in interconnected systems, power-aware networks will become part-and-parcel of many single-chip and multichip systems. As communication links consume significant power regardless of utilization, a mechanism to realize such power-aware networks is on/off links驴network links that can be turned on/off as a function of traffic. In this paper, we investigate and propose self-regulating power-aware interconnection networks that turn their links on/off in response to bursts and dips in traffic in a distributed fashion. We explore the design space of such on/off networks, outlining a 5-step design methodology along with various building block solutions at each step that can be effectively assembled to develop various on/off network designs. We applied our methodology to the design of two classes of on/off networks with links that possess substantially different on/off delays, an on-chip network as well as a chip-to-chip network, and show that our designs are able to adapt dynamically to variations in network traffic. Three specific network designs are then constructed, presented, and evaluated. Our simulations show that link power consumption can be reduced by up to 54.4 percent, with a modest increase in network latency.
机译：随着功耗在互连系统中变得越来越关键，功耗感知网络将成为许多单芯片和多芯片系统的组成部分。由于通信链路不考虑利用率而消耗大量功率，因此实现这种功率感知网络的机制是开/关链路，可以根据业务量开/关的驴网络链路。在本文中，我们研究并提出了自我调节的功率感知互连网络，该网络可以以分布式方式响应于流量的突发和骤降来打开/关闭其链路。我们探索了此类开/关网络的设计空间，概述了每个步骤的5步设计方法以及各种构建模块解决方案，这些方法可以有效地组装以开发各种开/关网络设计。我们将我们的方法论应用于两类通/断网络的设计，这些网络的链路具有明显不同的通/断延迟，该电路具有片上网络以及芯片到芯片网络，并且表明我们的设计能够动态适应网络流量的变化。然后构建，展示和评估三个特定的网络设计。我们的仿真表明，链路功耗可以降低多达54.4％，同时网络延迟会适度增加。

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