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Parallel Asynchronous Watershed Algorithm-Architecture

机译：并行异步分水岭算法体系结构

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摘要

A joint algorithm-architecture study has resulted into a new version of a picture segmentation system complying with multimedia mobile terminal constraints, i.e., real-time computing, and low power consumption. Previously published watershed segmentation algorithms required at least three global synchronization points: minima detection, labeling and flooding. This paper presents a new fully asynchronous algorithm, where pixels can compute their local data in parallel and independently from one another, and which requires only a unique final global synchronization point. This paper provides a formal demonstration of the convergence and correctness of this new parallel asynchronous algorithm using a mathematical model of data propagation in a graph: the associative net formalism. We demonstrate the simplicity of implementation of this algorithm on parallel processor arrays. We explore, simulate, and validate several configurations of the algorithm-architecture using a "SystemC" model. Simulations reveal an image segmentation rate up to 66,000 QCIF images/sec, i.e., a speed-up factor of more than 1,000 times compared with state of the art watershed algorithms. A fine grain processor array design using STmicroelectronics 0.18mum. CMOS technology confirms that this new approach is a breakthrough in the domain of real-time image segmentation
机译：联合算法-体系结构研究已经产生了符合多媒体移动终端约束（即实时计算和低功耗）的图片分割系统的新版本。先前发布的分水岭分割算法至少需要三个全局同步点：最小检测，标记和泛洪。本文提出了一种新的完全异步算法，其中像素可以并行且彼此独立地计算其本地数据，并且只需要一个唯一的最终全局同步点即可。本文使用图形中的数据传播数学模型：关联的网络形式主义，对这种新的并行异步算法的收敛性和正确性进行了形式化证明。我们演示了在并行处理器阵列上实现此算法的简单性。我们使用“ SystemC”模型探索，模拟和验证算法体系结构的几种配置。仿真揭示了高达66,000个QCIF图像/秒的图像分割率，即与现有技术的分水岭算法相比，其加速因子超过了1,000倍。使用意法半导体（STmicroelectronics）0.18μm的细晶粒处理器阵列设计。 CMOS技术证实了这种新方法是实时图像分割领域的突破

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