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Fault Tolerant Interleaved Switching Fabrics For Scalable High-Performance Routers

机译:可扩展高性能路由器的容错交错交换结构

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Scalable high performance routers and switches are required to provide a larger number of ports, higher throughput, and good reliability. Most of todayu00026;#8217;s routers and switches are implemented using single crossbar as the switched fabric. The single crossbar complexity increases at O(N2) in terms of crosspoint number, which might become unacceptable for scalability as the port number (N) increases. A delta class self-routing multistage interconnection network (MIN) with the complexity of O(N × log2N) has been widely used in the ATM switches. However, the reduction of the crosspoint number results in considerable internal blocking. A number of scalable methods have been proposed to solve this problem. One of them uses more stages with recirculation architecture to reroute the deflected packets, which greatly increase the latency. In this paper, we propose an interleaved multistage switching fabrics architecture and assess its throughput with an analytical model and simulations. We compare this novel scheme with some previous parallel architectures and show its benefits. From extensive simulations under different traffic patterns and fault models, our interleaved architecture achieves better performance than its counterpart of single panel fabric. Our interleaved scheme achieves speedups (over the single panel fabric) of 3.4 and 2.25 under uniform and hot-spot traffic patterns, respectively at maximum load (p=1). Moreover, the interleaved fabrics show great tolerance against internal hardware failures.
机译:需要可扩展的高性能路由器和交换机来提供更多的端口,更高的吞吐量和良好的可靠性。当今的大多数路由器和交换机都是使用单个交叉开关作为交换结构来实现的。单个交叉开关的复杂度在交叉点数处为O(N2),随着端口数(N)的增加,可伸缩性可能变得不可接受。复杂度为O(N×log2N)的增量类自路由多级互连网络(MIN)已广泛用于ATM交换机中。但是,交叉点数量的减少导致相当大的内部阻塞。已经提出了许多可扩展的方法来解决这个问题。其中之一使用具有再循环架构的更多级来重新路由偏转的数据包,这大大增加了延迟。在本文中,我们提出了一种交错的多级交换结构架构,并通过分析模型和仿真评估其吞吐量。我们将这种新颖的方案与以前的一些并行体系结构进行了比较,并显示了其好处。通过在不同的流量模式和故障模型下进行广泛的仿真,我们的交错体系结构可实现比单面板结构更好的性能。我们的交错方案在均匀和热点流量模式下分别在最大负载下(p = 1)分别实现3.4和2.25的加速比(在单面板结构上)。而且,交错结构对内部硬件故障表现出很大的容忍度。

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