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Hardware and compiler-directed cache coherence in large-scale multiprocessors: Design considerations and performance study

机译:大型多处理器中硬件和编译器控制的缓存一致性:设计注意事项和性能研究

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摘要

In this paper, we study a hardware-supported, compiler-directed (HSCD) cache coherence scheme, which can be implemented on a large-scale multiprocessor using off-the-shelf microprocessors, such as the Cray T3D. The scheme can be adapted to various cache organizations, including multiword cache lines and byte-addressable architectures. Several system related issues, including critical sections, interthread communication, and task migration have also been addressed. The cost of the required hardware support is minimal and proportional to the cache size. The necessary compiler algorithms, including intra- and interprocedural array data flow analysis, have been implemented on the Polaris parallelizing compiler. From our simulation study using the Perfect Club benchmarks, we found that in spite of the conservative analysis made by the compiler, for four of six benchmark programs tested, the proposed HSCD scheme outperforms the full-map hardware directory scheme up to 70 percent while the hardware scheme outperforms the HSCD scheme in the remaining two applications up to 89 percent. Given its comparable performance and reduced hardware cost, the proposed scheme can be a viable alternative for large-scale multiprocessors such as the Cray T3D, which rely on users to maintain data coherence.
机译:在本文中,我们研究了一种硬件支持的编译器定向(HSCD)缓存一致性方案,该方案可以使用大型微处理器(例如Cray T3D)在大型多处理器上实现。该方案可以适用于各种缓存组织,包括多字缓存行和字节可寻址体系结构。还解决了几个与系统相关的问题,包括关键部分,线程间通信和任务迁移。所需的硬件支持成本最小,并且与高速缓存大小成比例。必要的编译器算法,包括过程内和过程间数组数据流分析,已在Polaris并行化编译器上实现。通过使用Perfect Club基准进行的模拟研究,我们发现,尽管编译器进行了保守分析,但对于所测试的六个基准程序中的四个,拟议的HSCD方案的性能要比全图硬件目录方案高70%,而在其余两个应用程序中,硬件方案的性能优于HSCD方案,最高可达89%。考虑到其可比的性能和降低的硬件成本,对于依赖于用户保持数据一致性的大型多处理器(例如Cray T3D),该方案可以成为可行的替代方案。

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