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首页> 外文期刊>IEEE Transactions on Parallel and Distributed Systems >A scalable multibus configuration for connecting transputer links
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A scalable multibus configuration for connecting transputer links

机译：可扩展的多总线配置，用于连接晶片连接

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摘要

The paper presents the development and the performance of a novel bus based message passing interconnection scheme which can be used to join a large number of INMOS transputers via their serial communication links. The main feature of this architecture is that it avoids the communication overhead which occurs in systems where processing nodes relay communications to their neighbors. It also produces a flexible and scalable machine whose attractive characteristics are its simplicity and low latency for large configurations. We show that this architecture is free from deadlock, exhibits much smaller latency than most directly connected transputer networks and has a scalable bandwidth, in contrast to other bus topologies.
机译：本文介绍了一种新颖的基于总线的消息传递互连方案的开发和性能，该方案可用于通过其串行通信链路加入大量INMOS晶片机。该体系结构的主要特征是它避免了在处理节点将通信中继到其邻居的系统中发生的通信开销。它还生产了一种灵活且可扩展的机器，其吸引人的特点是其简单性和对大型配置的低延迟。我们证明，与其他总线拓扑结构相比，该体系结构没有死锁，与大多数直接连接的晶片机网络相比，延迟较小，并且具有可扩展的带宽。

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