首页> 外文期刊>IEEE Transactions on Parallel and Distributed Systems >A compile-time scheduling heuristic for interconnection-constrained heterogeneous processor architectures
【24h】

A compile-time scheduling heuristic for interconnection-constrained heterogeneous processor architectures

机译:针对互连受限的异构处理器体系结构的编译时调度启发式方法

获取原文
获取原文并翻译 | 示例
           

摘要

The authors present a compile-time scheduling heuristic called dynamic level scheduling, which accounts for interprocessor communication overhead when mapping precedence-constrained, communicating tasks onto heterogeneous processor architectures with limited or possibly irregular interconnection structures. This technique uses dynamically-changing priorities to match tasks with processors at each step, and schedules over both spatial and temporal dimensions to eliminate shared resource contention. This method is fast, flexible, widely targetable, and displays promising performance.
机译:作者提出了一种称为动态级别调度的编译时调度启发式方法,该方法在将优先级受限的通信任务映射到具有有限或可能不规则互连结构的异构处理器体系结构时,解决了处理器间的通信开销。该技术使用动态更改的优先级来在每个步骤将任务与处理器进行匹配,并在空间和时间维度上进行调度以消除共享资源争用。这种方法快速,灵活,可针对性强,并显示出令人鼓舞的性能。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号