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An optimal implementation of broadcasting with selective reduction

机译：选择性减少广播的最佳实现

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摘要

A model of parallel computation called broadcasting with selective reduction (BSR) can be viewed as a concurrent-read concurrent-write (CRCW) parallel random access machine (PRAM) with one extension. An additional type of concurrent memory access is permitted in BSR, namely the BROADCAST instruction by means of which all N processors may gain access to all M memory locations simultaneously for the purpose of writing. At each memory location, a subset of the incoming broadcast data is selected and reduced to one value finally stored in that location. For several problems, BSR algorithms are known which require fewer steps than the corresponding best-known PRAM algorithms, using the same number of processors. A circuit is introduced to implement the BSR model, and it is shown that, in size and depth, the circuit presented is of the same order as an optimal circuit implementing the PRAM. Thus, if it is reasonable to assume that CRCW PRAM instructions execute in constant time, the assumption of a constant time BROADCAST instruction is no less reasonable.
机译：可以将并行计算模型称为“选择性缩减广播”（BSR），将其视为具有一个扩展的并发读取并发写入（CRCW）并行随机存取机（PRAM）。 BSR中允许使用其他类型的并发存储器访问，即BROADCAST指令，所有N个处理器都可以通过该指令同时访问所有M个存储器位置以进行写入。在每个存储位置，选择传入广播数据的子集并将其减少到最终存储在该位置的一个值。对于几个问题，使用相同数量的处理器的BSR算法比相应的最著名的PRAM算法需要更少的步骤。介绍了一种电路来实现BSR模型，结果表明，在大小和深度上，所示电路与实现PRAM的最佳电路的顺序相同。因此，如果合理地假设CRCW PRAM指令在恒定时间内执行，则恒定时间BROADCAST指令的假设同样合理。

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