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DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory

机译:Detras:在硬件交易记忆中延迟友好消防的商店

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Commercial Hardware Transactional Memory (HTM) systems are best-effort designs that leverage the coherence substrate to detect conflicts eagerly. Resolving conflicts in favor of the requesting core is the simplest option for ensuring deadlock freedom, yet it is prone to livelocks. In this work, we propose and evaluate DeTraS (Delayed Transactional Stores), an HTM-aware store buffer design aimed at mitigating such livelocks. DeTraS takes advantage of the fact that modern commercial processors implement a large store buffer, and uses it to prevent transactional stores predicted to conflict from performing early in the transaction. By leveraging existing processor structures, we propose a simple design that improves the ability of requester-wins HTM systems to achieve forward progress in spite of high contention while side-stepping the performance penalty of falling back to mutual exclusion. With just over 50 extra bytes, DeTraS captures the advantages of lazy conflict management without the complexity brought into the coherence fabric by commit arbitration schemes nor the relaxation of the single-writer invariant of prior works. Through detailed simulations of a 16-core tiled CMP using gem5, we demonstrate that DeTraS brings reductions in average execution time of 25 percent when compared to an Intel RTM-like design.
机译:商业硬件交易记忆(HTM)系统是最佳精力设计,其利用相干基板热切地检测冲突。解决有利于请求核心的冲突是确保死锁自由的最简单选择,但它易于生活。在这项工作中,我们提出并评估了Detras(延迟的交易商店),这是一个旨在减轻这种固定的HTM感知商店缓冲区设计。 Detras利用现代商业处理器实现大型商店缓冲区的事实,并使用它来防止预测发生冲突的事务存储在交易早期进行冲突。通过利用现有的处理器结构,我们提出了一种简单的设计,可以提高请求者 - 赢得HTM系统在依靠高争用的情况下实现前进进展的能力,同时踩回倒回相互排斥的绩效惩罚。只需50多个额外的字节,Detras捕获了懒惰冲突管理的优势,而不通过提交仲裁计划带入一致性面料的复杂性,也不放松先前作品的单一作者不变。通过使用GEM5的16核平铺CMP的详细模拟,我们证明了与Intel RTM的设计相比,Detras在平均执行时间内降低了25%的平均执行时间。

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