A procedure for designing a novel HVDC current controller is presented. The proposed controller makes HVDC system performance less prone to fundamental frequency oscillations on a DC line, and thus less susceptible to the second harmonic instability. The design is based on a linearised AC/DC system model and on the pole-placement technique. Controller performance is tested against the CIGRE HVDC Benchmark model using the EMTDC/PSCAD simulation package. It is demonstrated that this controller eliminates the dominant oscillatory mode on the DC side, and that it gives a significant improvement in system response even for low SCR AC systems.
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