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首页> 外文期刊>Power Electronics, IET >Active stabilisation design of DC–DC converters with constant power load using a sampled discrete-time model: stability analysis and experimental verification
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Active stabilisation design of DC–DC converters with constant power load using a sampled discrete-time model: stability analysis and experimental verification

机译：使用采样离散时间模型的恒功率负载DC-DC转换器的主动稳定设计：稳定性分析和实验验证

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摘要

Instabilities of cascade converters with an LC filter in between in power electronic systems have been known, and many answers have been proposed. The load converters are tightly regulated, acting as constant power loads (CPLs). Average models are generally utilised to study the behavior of the converters. For embedded applications, the weight and the volume should be reduced. Consequently, in this case, the limitations of the average method are reached when the cut-off frequency of the LC input filter is close to the switching frequency. Then, other tools are necessary to study this type of system. To overcome this problem, a discrete-time model was developed to study the behavior of the system, taking into account the switching effect. The aim was to enlarge the power range of the stability zone for a DC system composed of a DC-DC boost converter as a source converter, which was connected to the power load via an LC input filter. For this purpose, a stabilisation expression is integrated in the command of the source converter. The stability analysis by the eigenvalues of the system is described using the proposed model. Simulation and experimental results are discussed to verify the proposed stabiliser in different cases.
机译：在电力电子系统中，具有LC滤波器的级联转换器的不稳定性是已知的，并且已经提出了许多答案。负载转换器经过严格调节，用作恒定功率负载（CPL）。通常使用平均模型来研究转换器的行为。对于嵌入式应用，应减少重量和体积。因此，在这种情况下，当LC输入滤波器的截止频率接近开关频率时，就达到了平均方法的局限性。然后，需要其他工具来研究这种类型的系统。为了克服这个问题，开发了一个离散时间模型来研究系统的行为，同时考虑了切换效果。目的是扩大由DC-DC升压转换器作为源转换器组成的DC系统的稳定区的功率范围，该DC-DC升压转换器通过LC输入滤波器连接到功率负载。为此，将稳定表达式集成在源转换器的命令中。使用提出的模型描述了系统特征值的稳定性分析。讨论了仿真和实验结果，以验证在不同情况下提出的稳定器。

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