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首页> 外文期刊>Power Electronics, IET >Analysis of THD and output voltage performance for cascaded multilevel inverter using carrier pulse width modulation techniques
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Analysis of THD and output voltage performance for cascaded multilevel inverter using carrier pulse width modulation techniques

机译：使用载波脉冲宽度调制技术分析级联多电平逆变器的THD和输出电压性能

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摘要

Multilevel inverter is used in applications that need high voltage and high current. The topologies of multilevel inverter have several advantages such as lower total harmonic distortion (THD), lower electro magnetic interference (EMI) generation, high output voltage. The main feature of multilevel inverter is the ability to reduce the voltage stress on each power device due to the utilisation of multilevel on the DC bus. The advent of multilevel inverter topologies has caused variety of pulse width modulation strategies. In this paper, various carrier pulse width modulation techniques are proposed, which can minimise the total harmonic distortion and enhances the output voltages from five level inverter. Three methodologies adopting the constant switching frequency (CSF), variable switching frequency (VSF), and phase shifted pulse width modulation (PSPWM) concepts are proposed in this paper. The above methodologies divided into two techniques like subharmonic pulse width modulation which minimises total harmonic distortion and switching frequency optimal pulse width modulation which enhances the output voltages. Field programmable gate array (FPGA) has been chosen to implement the pulse width modulation due its fast proto typing, simple hardware and software design. The simulation and experimental results are presented.Multilevel inverter is used in applications that need high voltage and high current. The topologies of multilevel inverter have several advantages such as lower total harmonic distortion (THD), lower electro magnetic interference (EMI) generation, high output voltage. The main feature of multilevel inverter is the ability to reduce the voltage stress on each power device due to the utilisation of multilevel on the DC bus. The advent of multilevel inverter topologies has caused variety of pulse width modulation strategies. In this paper, various carrier pulse width modulation techniques are proposed, which can minimise the total harmonic distortion an-nd enhances the output voltages from five level inverter. Three methodologies adopting the constant switching frequency (CSF), variable switching frequency (VSF), and phase shifted pulse width modulation (PSPWM) concepts are proposed in this paper. The above methodologies divided into two techniques like subharmonic pulse width modulation which minimises total harmonic distortion and switching frequency optimal pulse width modulation which enhances the output voltages. Field programmable gate array (FPGA) has been chosen to implement the pulse width modulation due its fast proto typing, simple hardware and software design. The simulation and experimental results are presented.
机译：多电平逆变器用于需要高电压和高电流的应用中。多电平逆变器的拓扑具有多个优势，例如更低的总谐波失真（THD），更低的电磁干扰（EMI）产生，高输出电压。多电平逆变器的主要特点是能够减少由于直流母线上的多电平而导致的每个功率设备上的电压应力。多级逆变器拓扑的出现已经导致了多种脉冲宽度调制策略。本文提出了多种载波脉宽调制技术，可以最大程度地减小总谐波失真并提高五电平逆变器的输出电压。提出了采用恒定开关频率（CSF），可变开关频率（VSF）和相移脉宽调制（PSPWM）概念的三种方法。上面的方法分为两种技术，例如使总谐波失真最小的亚谐波脉冲宽度调制和增强输出电压的开关频率最佳脉冲宽度调制。由于其快速的原型输入，简单的硬件和软件设计，已选择现场可编程门阵列（FPGA）来实现脉冲宽度调制。给出了仿真和实验结果。多电平逆变器用于需要高电压和高电流的应用中。多电平逆变器的拓扑具有多个优势，例如更低的总谐波失真（THD），更低的电磁干扰（EMI）产生，高输出电压。多电平逆变器的主要特点是能够减少由于直流母线上的多电平而导致的每个功率设备上的电压应力。多级逆变器拓扑的出现已经导致了多种脉冲宽度调制策略。本文提出了多种载波脉宽调制技术，可以最大程度地减小总谐波失真，并提高五电平逆变器的输出电压。提出了采用恒定开关频率（CSF），可变开关频率（VSF）和相移脉宽调制（PSPWM）概念的三种方法。上面的方法分为两种技术，例如使总谐波失真最小的亚谐波脉冲宽度调制和增强输出电压的开关频率最佳脉冲宽度调制。由于其快速的原型输入，简单的硬件和软件设计，已选择现场可编程门阵列（FPGA）来实现脉冲宽度调制。给出了仿真和实验结果。

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  • 来源
    《Power Electronics, IET》 |2011年第8期|p.951-958|共8页
  • 作者

    Palanivel P.; Dash S.S.;

  • 作者单位

    SRM University, EEE, Kattankulathur, Chennai 603203, Tamilnadu, India;

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