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首页> 外文期刊>Proceedings of the IEEE >Technology challenges for integration near and below 0.1 /spl mu/m
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Technology challenges for integration near and below 0.1 /spl mu/m

机译：接近和低于0.1 / spl mu / m的集成技术挑战

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摘要

Technology challenges for silicon integrated circuits with a design rule of 0.1 /spl mu/m and below are addressed. We begin by reviewing the state-of-the-art CMOS technology at 0.25 /spl mu/m currently in development, covering a logic-oriented processes and dynamic random access memory (DRAM) processes. CMOS transistor structures are compared by introducing a figure of merit. We then examine scaling guidelines for 0.1 /spl mu/m which has started to deviate for optimized performance from the classical theory of constant-field scaling. This highlights the problem of nontrivial subthreshold current associated with the scaled-down CMOS with low threshold voltages. Interconnect issues are then considered to assess the performance of microprocessors in 0.1 /spl mu/m technology. 0.1 /spl mu/m technology will enable a microprocessor which runs at 1000 MHz with 500 million transistors. Challenges below 0.1 /spl mu/m are then addressed. New transistor and circuit possibilities such as silicon on insulator (SOI), dynamic-threshold (DT) MOSFET, and back-gate input MOS (BMOS) are discussed. Two problems below 0.1 /spl mu/m are highlighted. They are threshold voltage control and pattern printing. It is pointed out that the threshold voltage variations due to doping fluctuations is a limiting factor for scaling CMOS transistors for high performance. The problem with lithography below 0.1 /spl mu/m is the low throughput for a single probe. The use of massively parallel scanning probe assemblies working over the entire wafer is suggested to overcome the problem of low throughput.
机译：解决了设计规则为0.1 / spl mu / m及以下的硅集成电路的技术挑战。我们首先以当前正在开发的0.25 / spl mu / m的先进CMOS技术进行回顾，涵盖了面向逻辑的过程和动态随机存取存储器（DRAM）过程。通过引入品质因数比较CMOS晶体管结构。然后，我们检查0.1 / spl mu / m的缩放准则，该准则已开始偏离经典的恒定场缩放理论以优化性能。这突出了与具有低阈值电压的按比例缩小的CMOS相关的不平凡的亚阈值电流的问题。然后考虑互连问题，以评估0.1 / spl mu / m技术中的微处理器的性能。 0.1 / spl mu / m技术将使微处理器以5亿个晶体管在1000 MHz下运行。然后解决低于0.1 / spl mu / m的挑战。讨论了新的晶体管和电路可能性，例如绝缘体上硅（SOI），动态阈值（DT）MOSFET和背栅输入MOS（BMOS）。突出显示了低于0.1 / spl mu / m的两个问题。它们是阈值电压控制和图案打印。应当指出，由于掺杂波动引起的阈值电压变化是缩放CMOS晶体管以实现高性能的限制因素。低于0.1 / spl mu / m的光刻问题是单个探针的生产量低。建议使用在整个晶片上工作的大规模并行扫描探针组件来克服低通量的问题。

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