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首页> 外文期刊>Pomiary Automatyka Kontrola >The versatile hardware accelerator framework for sparse vector calculations
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The versatile hardware accelerator framework for sparse vector calculations

机译：用于稀疏矢量计算的通用硬件加速器框架

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摘要

In this paper, we present the advantage of the ability of FPGAs to perform various computationally complex calculations using deep pipelining and parallelism. We propose an architecture that consists of many small stream processing blocks. The designed framework maintains proper data movement and synchronization. The architecture can be easily adapted to be implemented in FPGA devices of a various size and cost - from small SoC devices to high-end PCIe accelerator cards. It is capable to perform a selected operation on a sparse data that are loaded as the stream of vectors. As an example application, we have implemented the cosine similarity measure for the text similarity calculations that uses the TF-IDF weighting scheme. The presented example application calculates the similarity of texts from the set of input documents to documents from the large database. The scheme is used to find the most similar documents. The proposed design can decrease the service time of search queries in computer centers while reducing power consumption.
机译：在本文中，我们展示了FPGA能够利用深度流水线技术和并行性执行各种计算复杂的计算的优势。我们提出了一种由许多小型流处理模块组成的体系结构。设计的框架保持适当的数据移动和同步。从小型SoC器件到高端PCIe加速器卡，该体系结构可以轻松地实现在各种尺寸和成本的FPGA器件中实施。它能够对作为矢量流加载的稀疏数据执行选定的操作。作为示例应用程序，我们为使用TF-IDF加权方案的文本相似度计算实现了余弦相似度度量。呈现的示例应用程序计算输入文档集中文本与大型数据库文档之间的相似度。该方案用于查找最相似的文档。所提出的设计可以减少计算机中心搜索查询的服务时间，同时降低功耗。

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