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首页> 外文期刊>Sensing and imaging >FPGA Implementation of Balanced Biorthogonal Multiwavelet Using Direct Pipelined Mapping Method for Image Compression Applications
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FPGA Implementation of Balanced Biorthogonal Multiwavelet Using Direct Pipelined Mapping Method for Image Compression Applications

机译：用于图像压缩应用的直接流水线映射方法的平衡双正交多小波的FPGA实现

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摘要

An area-competent and low power pipelined direct mapping Very Large-Scale IntegrationArchitecture for multidimensional (2D) balanced biorthogonal wavelets forimage compression is discussed. The 2D architecture is realized by cascading two Npoints (1-D) owing to linearity, balance, and compact support of the multi-dimensionalityof the biorthogonal wavelet. The discrete wavelet transforms for a 2-dimensionalwith balanced wavelet has been structured utilizing MATLAB program forindividual modules like forwarding balanced Wavelet Transform and Inverse balancedWavelet Transform to establish the peak signal to noise ratio (PSNR), correlationin between the recovered image and input image. The architectures aredesigned using Xilinx SYSgen and implemented in the Zynq 7000S devices featurea single-core ARM Cortex™-A9 processor mated with 28 nm Artix®-7 based programmablelogic processor. Implementation results indicate the compression ratio isincreased with less PSNR and also increases in speed with low power.
机译：一个区域竞争力和低功耗的流水线直接映射非常大的集成多维（2D）平衡双正交小波的体系结构讨论图像压缩。通过级联两个n实现2D架构由于线性，平衡和多维量的紧凑支持，点（1-D）双正交小波。离散小波变换为二维使用MATLAB计划的平衡小波构造了单个模块，如转发平衡小波变换和反向平衡小波变换建立峰值信号到噪声比（PSNR），相关性在恢复的图像和输入图像之间。架构是使用Xilinx Sysgen设计并在Zynq 7000S设备中实现单芯臂Cortex™-A9处理器配有28 NMArtix®-7基于可编程的可编程逻辑处理器。实施结果表明压缩比是随着PSNR较少而增加，并且速度较低，功率低。

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