Performance evaluation of a third-order LADF sigma-delta (Σ-Δ) modulator via FPGA implementation

Saman S. Abeysekera; Charayaphan Charoensak

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Performance evaluation of a third-order LADF sigma-delta (Σ-Δ) modulator via FPGA implementation

机译：通过FPGA实现对三阶LADFΣ-Δ（Σ-Δ）调制器的性能评估

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摘要

Over the last few decades, sigma-delta (Σ-Δ) modulators have been widely used in various signal processing applications. In these applications, for improved signal-to-noise ratio performances, higher order modulators are used. In this paper, we investigate the performance of a third-order Look Ahead Decision Feedback (LADF) Σ-Δ modulator. It is shown that the LADF Σ-Δ modulator, which has not been widely reported in the literature, is efficient and offers attractive features for hardware implementation. These features are investigated via the use of a system level design for Field Programmable Gate Array prototyping of the LADF modulator.

机译：在过去的几十年中，sigma-delta（Σ-Δ）调制器已广泛用于各种信号处理应用中。在这些应用中，为了提高信噪比性能，使用了高阶调制器。在本文中，我们研究了三阶超前决策反馈（LADF）Σ-Δ调制器的性能。结果表明，尚未在文献中广泛报道的LADFΣ-Δ调制器高效且为硬件实现提供了诱人的功能。通过使用系统级设计对LADF调制器进行现场可编程门阵列原型设计，可以研究这些功能。

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来源
《Signal processing》 |2007年第1期|p.162-176|共15页
作者
Saman S. Abeysekera; Charayaphan Charoensak;
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作者单位

Block S2.1, School of Electrical & Electronic Engineering, Nanyang Technological University, Nanyang Avenue, Singapore 639798;

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原文格式 PDF
正文语种 eng
中图分类通信;
关键词
sigma-delta modulators; LADF; FPGA;

机译：sigma-delta调制器;LADF;FPGA;

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Performance evaluation of a third-order LADF sigma-delta (Σ-Δ) modulator via FPGA implementation

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