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Design Considerations of a Fault Current Limiting Dynamic Voltage Restorer (FCL-DVR)

机译:故障限流动态电压恢复器(FCL-DVR)的设计注意事项

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摘要

This paper proposes a new fault current limiting dynamic voltage restorer (FCL-DVR) concept. The new topology uses a crowbar bidirectional thyristor switch across the output terminals of a conventional back-to-back DVR. In the event of a load short, the DVR controller will deactivate the faulty phase of the DVR and activate its crowbar thyristor to insert the DVR filter reactor into the grid to limit the fault current. A fault condition is detected by sensing the load current and its rate of change. The FCL-DVR will operate with different protection strategies under different fault conditions. Design of the FCL-DVR involves selecting important parameters, such as DVR power rating, dc link voltage of the DVR, output filter reactors and capacitors, and grid-tied transformers is proposed. The design methodology of the proposed FCL-DVR is fully discussed based on power systems computer aided design (PSCAD)/electromagnetic transients including dc (EMTDC) simulation. A scaled-down experimental verification is also carried out. Both modeling and experimental results confirm the effectiveness of the new FCL-DVR concept for performing both voltage compensation and fault current limiting functions.
机译:本文提出了一种新的故障电流限制动态电压恢复器(FCL-DVR)概念。新的拓扑结构在传统背靠背DVR的输出端子之间使用撬棍双向晶闸管开关。在负载短路的情况下,DVR控制器将停用DVR的故障相位,并激活其撬棍可控硅,以将DVR滤波电抗器插入电网以限制故障电流。通过检测负载电流及其变化率来检测故障状态。 FCL-DVR将在不同的故障条件下以不同的保护策略运行。 FCL-DVR的设计涉及选择重要的参数,例如DVR的额定功率,DVR的直流链路电压,输出滤波电抗器和电容器以及并网变压器。基于电力系统计算机辅助设计(PSCAD)/包括直流电(EMTDC)仿真的电磁瞬态,对所提出的FCL-DVR的设计方法进行了全面讨论。还进行了按比例缩小的实验验证。建模和实验结果均证实了新型FCL-DVR概念在执行电压补偿和故障电流限制功能方面的有效性。

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