Design considerations for high-frequency CMOS continuous-time current-mode filters are presented. The basic building block is a differential current integrator with its gain constant set by a small-signal transconductance and a gate capacitance. A prototype fifth-order low-pass ladder filter implemented in a standard digital 2 mu m n-well CMOS process achieved a -3 dB cutoff frequency (f/sub 0/) of 42 MHz; f/sub 0/ was tunable from 24 to 42 MHZ by varying a reference bias current from 50 to 150 mu A. Using a single 5 V power supply with a nominal reference current of 100 mu A, the five-pole filter dissipated 25.5 mW. The active filter area was 0.056 mm/sup 2//pole. With the minimum input signal defined as the input-referred noise integrated over a 40 MHz bandwidth, and the maximum input signal defined at the 1% total intermodulation distortion (TIMD) level, the measured dynamic range was 69 dB. A third-order elliptic low-pass ladder filter was also integrated in the 2 mu m n-well CMOS process to verify the implementation of finite transmission zeros.
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机译：提出了高频CMOS连续时间电流模式滤波器的设计注意事项。基本模块是差分电流积分器，其增益常数由小信号跨导和栅极电容设置。采用标准的数字2微米n阱CMOS工艺实现的原型五阶低通梯形滤波器实现了42 MHz的-3 dB截止频率（f / sub 0 /）。通过将参考偏置电流从50改变为150μA，可以将f / sub 0 /从24 MHZ调谐到42 MHZ。使用标称参考电流为100μA的5 V单电源，五极滤波器的功耗为25.5 mW 。有源滤波器面积为0.056 mm / sup 2 // pole。将最小输入信号定义为在40 MHz带宽上积分的输入参考噪声，将最大输入信号定义为总互调失真（TIMD）电平为1％时，测得的动态范围为69 dB。在2微米n阱CMOS工艺中还集成了三阶椭圆低通梯形滤波器，以验证有限传输零点的实现。
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