Four image reorganization ICs that enable real-time difference encoding for hierarchical lossless image compression are reported. Two image reorganization processors are realized on the focal-plane and two are designed for hybridization to a separate imager IC. The two focal-plane ICs represent the first integration of a 256*256 buried-channel frame-transfer CCD image sensor with additional charge-domain circuitry to enable image reformatting at video rates (28 frames/s). The four ICs generate pyramidal pixel output in 3*3 blocks with the center pixel first. Pixel data reorganization is performed through simultaneous readout of three rows of data, followed by pixel resequencing and sampling to provide differential output. A novel architecture provides simultaneous readout of multiple imager rows on the focal-plane ICs. The ICs have achieved a charge-transfer efficiency (CTE) of 0.99996 in the conventional horizontal and vertical CCD registers, and a CTE of 0.99994 in the SP/sup 3/ registers.
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