...
首页> 外文期刊>IEEE Journal of Solid-State Circuits >Advanced integrated-circuit reliability simulation including dynamic stress effects
【24h】

Advanced integrated-circuit reliability simulation including dynamic stress effects

机译:先进的集成电路可靠性仿真,包括动态应力效应

获取原文
获取原文并翻译 | 示例
           

摘要

A systematic approach to predict semiconductor degradation effects using reliability simulation is described. The DC degradation monitor is first extracted during transient circuit simulation. An AC degradation factor is then used to determine circuit performance degradation. By using these techniques on the design of CMOS components, proper long-term reliability can be achieved for high-speed circuits. Experimental results on digital circuits using an industrial submicrometer technology demonstrate the effectiveness of this approach in reliable VLSI circuit design. Results on two-input NAND gates, DRAM precharging circuit, and SRAM control circuits are presented.
机译:描述了使用可靠性仿真预测半导体退化效应的系统方法。首先在瞬态电路仿真过程中提取DC降级监控器。然后,将交流降级系数用于确定电路性能降级。通过在CMOS组件的设计中使用这些技术,可以为高速电路获得适当的长期可靠性。使用工业亚微米技术的数字电路实验结果证明了该方法在可靠的VLSI电路设计中的有效性。给出了两输入与非门,DRAM预充电电路和SRAM控制电路的结果。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号