The latch bus driver system

Leilich N.-O.; Dolle M.

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The latch bus driver system

机译：闩锁总线驱动器系统

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A large and growing fraction of the power in modern VSLI chips is dissipated by the drivers of external bus lines. A novel bus system drastically reduces power and noise by using a central driver chip which periodically attempts to charge and to discharge the bus lines. The transmitters of the selected chip inhibit the charge process for the establishment of a 'low' signal. The central driver latches the signal state after the inhibit phase. The authors explain the inhibit driver principle in comparison with the usual push-pull system, present the timing characteristics, and report on the design and the measured results of an experimental central driver chip in full-custom CMOS.

机译：外部总线驱动器消耗了现代VSLI芯片中越来越大的功率。一种新颖的总线系统通过使用中央驱动器芯片来大幅度降低功率和噪声，该驱动器芯片会定期尝试对总线进行充电和放电。所选芯片的发射器禁止充电过程以建立“低”信号。在禁止阶段之后，中央驱动器锁存信号状态。与常规推挽系统相比，作者解释了抑制驱动器原理，介绍了时序特性，并报告了全定制CMOS实验中央驱动器芯片的设计和测量结果。

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来源
《IEEE Journal of Solid-State Circuits》 |1991年第7期|P.995-1002|共8页
作者
Leilich N.-O.; Dolle M.;
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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类一般性问题;基本电子电路;
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The latch bus driver system

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