Wide-band symmetrical analog multiplier IC for coherent optical-fiber receivers operating up to 10 Gb/s

Rein H.-M.; Schmidt L.

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Wide-band symmetrical analog multiplier IC for coherent optical-fiber receivers operating up to 10 Gb/s

机译：宽带对称模拟乘法器IC，用于运行速度高达10 Gb / s的相干光纤接收器

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A versatile analog four-quadrant multiplier IC with large bandwidth (DC to 6 GHz and 10 Gb/s) and large dynamic range is presented. It was mainly developed for differential-phase-shift-keying (DPSK) phase demodulator and polarization diversity receivers in coherent optical-fiber transmission systems. The circuit consumes 450 mW and only needs a single power supply of -5 V. The circuit principle used allows exact symmetry with respect to both linear inputs, which reduced multiplication errors. In the intended application, especially, the time jitter and the offset voltage of the output pulse patterns are reduced to negligible values. The IC was realized in a 1.25- mu m double-polysilicon bipolar technology.

机译：提出了具有大带宽（DC至6 GHz和10 Gb / s）和大动态范围的通用模拟四象限乘法器IC。它主要用于相干光纤传输系统中的差分相移键控（DPSK）相位解调器和偏振分集接收机。该电路功耗为450 mW，仅需一个-5 V的单电源。所使用的电路原理就两个线性输入而言可实现精确的对称性，从而减少了乘法误差。特别地，在预期的应用中，时间抖动和输出脉冲图案的偏移电压减小到可以忽略的值。该集成电路采用1.25微米的双多晶硅双极技术实现。

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来源
《IEEE Journal of Solid-State Circuits》 |1991年第12期|P.1840-1846|共7页
作者
Rein H.-M.; Schmidt L.;
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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类一般性问题;基本电子电路;
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专利

1. Optical Coherent Receiver With a Switchable Electrical Dispersion Compensator for 10 Gb/s DPSK Transmission up to 300 km of SSMF in Metro Optical Networks [J] . Bhandare S., Joshi A., Becker D. Lightwave Technology, Journal of . 2010,第1期

机译：光学相干接收器，具有可切换的电弥散补偿器，可在城域光网络中以10 Gb / s的DPSK传输长达300 km的SSMF
2. A 10 Gb/s Hybrid ADC-Based Receiver With Embedded Analog and Per-Symbol Dynamically Enabled Digital Equalization [J] . Ayman Shafik, Ehsan Zhian Tabasy, Shengchang Cai, IEEE Journal of Solid-State Circuits . 2016,第3期

机译：基于10 Gb / s混合ADC的接收器，具有嵌入式模拟和每个符号动态启用的数字均衡
3. Design and Implementation of 10-Gb/s Optical Receiver Analog Front-End in 0.13-μm CMOS Technology [J] . Won-Seok OH, rnKang-Yeob PARK, rnKyu-Ho PARK, IEICE Transactions on Electronics . 2010,第3期

机译：采用0.13μmCMOS技术的10 Gb / s光接收器模拟前端的设计与实现
4. A Symmetrical Analog Wide-band Multiplier IC Operating Up To 8Gb/s [C] . Rein, H., Schmidt, . 1991

机译：对称模拟宽带乘法器IC，工作速率高达8Gb / s
5. Design techniques and implementations of high-speed analog communication circuits: Two analog-to-digital converters and a 3.125Gb/s receiver. [D] . Younis, Ahmed Abdell-Ra'oof. 2001

机译：高速模拟通信电路的设计技术和实现：两个模数转换器和一个3.125Gb / s接收器。
6. Comparing Areas under the Receiver Operating Characteristic Curves: The Potential Impact of the Last Experimentally Measured Operating Point [O] . David Gur, Andriy I. Bandos, Howard E. Rockette -1

机译：接收器工作特性曲线下的面积比较：最后一次实验测量的工作点的潜在影响
7. A 32x10 Gb/s OLT using a single ultra-wide bandwidth dual local oscillator coherent receiver [O] . Domanic¸ Lavery, Lidia Galdino, Zhixin Liu, 2017

机译：使用单个超宽带宽双本地振荡器相干接收器的32x10 GB / s OLT

Wide-band symmetrical analog multiplier IC for coherent optical-fiber receivers operating up to 10 Gb/s

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