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首页> 外文期刊>Solid-State Circuits, IEEE Journal of >A 5-GHz Direct Digital Frequency Synthesizer Using an Analog-Sine-Mapping Technique in 0.35- $mu$m SiGe BiCMOS
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A 5-GHz Direct Digital Frequency Synthesizer Using an Analog-Sine-Mapping Technique in 0.35- $mu$m SiGe BiCMOS

机译:使用模拟正弦映射技术的5GHz直接数字频率合成器,采用0.35- <公式FormulaType =“ inline”> $ mu $ m SiGe BiCMOS

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摘要

A direct digital frequency synthesizer (DDFS) using an analog-sine-mapping technique is presented in a 0.35-$mu{hbox{m}}$ SiGe BiCMOS process. We intend to apply the translinear principle to develop a triangle-to-sine converter (TSC) that can achieve outputs with low harmonic content. The TSC is introduced for the DDFS to translate phase data to sine wave. Using this analog-interpolating technique, the DDFS, with 9 bits of phase resolution and 8 bits of amplitude resolution, can achieve operation at 5-GHz clock frequency and can further reduce power consumption and die area. The spurious-free dynamic range (SFDR) of the DDFS is better than 48 dBc at low synthesized frequencies, decreasing to 45.7 dBc worst case at the Nyquist synthesized frequency for output frequency band (0–2.5 GHz). The DDFS consumes 460 mW at a 3.3-V supply and achieves a high power efficiency figure of merit (FOM) of 10.87 GHz/W. The chip occupies $1.5times 1.4 {hbox{mm}}^{2}$ .
机译:使用模拟正弦映射技术的直接数字频率合成器(DDFS)显示在0.35- <公式Formulatype =“ inline”> $ mu {hbox {m}} $ SiGe BiCMOS工艺。我们打算应用跨线性原理来开发可实现低谐波含量输出的三角到正弦转换器(TSC)。为DDFS引入了TSC,将相位数据转换为正弦波。使用这种模拟插值技术,具有9位相位分辨率和8位幅度分辨率的DDFS可以在5 GHz时钟频率下工作,并且可以进一步降低功耗和芯片面积。在低合成频率下,DDFS的无杂散动态范围(SFDR)优于48 dBc,在输出频带(0–2.5 GHz)的Nyquist合成频率下,最差情况降至45.7 dBc。 DDFS在3.3V电源下的功耗为460mW,并实现了10.87 GHz / W的高功率效率品质因数(FOM)。芯片占用 $ 1.5 x 1.4 {hbox {mm}} ^ {2} $

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