Delay models and speed improvement techniques for RC tree interconnections among small-geometry CMOS inverters

Wu C.-Y.; Shiau M.-C.

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Delay models and speed improvement techniques for RC tree interconnections among small-geometry CMOS inverters

机译：小尺寸CMOS反相器之间RC树互连的延迟模型和速度改进技术

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Physical delay models entirely based upon device equations for small-geometry CMOS inverters with RC tree interconnection networks are presented. Through extensive comparisons with SPICE simulation results, it is shown that the maximum relative error in delay-time calculations using the developed model is within 15% for 1.5- mu m CMOS inverters with RC tree interconnection networks. An experimental sizing program is constructed for speed improvement of interconnection lines and trees. In this program, given the size of the input logic gate and its driving interconnection resistances, capacitances, and structures, users can choose one of four speed-improvement techniques and determine the suitable sizes and/or number of drivers/repeaters for a minimum delay. The four speed-improvement techniques use minimum-size repeaters and cascaded input drivers to reduce the interconnection delay. It is found that the required tapering factor in cascaded drivers is not the base of the natural logarithm, but a value in the range 4-8. Adding a small number of drivers/repeaters with large sizes reduces the interconnection delay more efficiently.

机译：提出了完全基于带有RC树互连网络的小几何CMOS反相器器件方程的物理延迟模型。通过与SPICE仿真结果进行大量比较，结果表明，对于使用RC树互连网络的1.5μmCMOS逆变器，使用开发的模型计算的延迟时间中的最大相对误差在15％以内。构建了一个实验性的尺寸确定程序，以加快互连线和树木的速度。在此程序中，考虑到输入逻辑门的大小及其驱动互连电阻，电容和结构，用户可以选择四种速度改进技术之一，并确定驱动器/中继器的合适大小和/或数量，以最大程度地减少延迟。四种速度改进技术使用最小尺寸的中继器和级联的输入驱动器来减少互连延迟。发现级联驱动程序中所需的渐缩因子不是自然对数的底，而是4-8范围内的值。添加少量的大尺寸驱动器/中继器可以更有效地减少互连延迟。

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《IEEE Journal of Solid-State Circuits》 |1990年第5期|P.1247-1256|共10页
作者
Wu C.-Y.; Shiau M.-C.;
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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类一般性问题;基本电子电路;
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1. Power dissipation models and performance improvement techniques for CMOS inverters with RC line and tree interconnections [J] . Tang H.-C., Shiau M.-C. IEE Proceedings. Part G, Circuits, Devices and Systems . 1993,第6期

机译：具有RC线和树形互连的CMOS逆变器的功耗模型和性能改进技术
2. The signal delay in interconnection lines considering the effects of small-geometry CMOS inverters [J] . Shiau M.-C., Wu C.-Y. IEEE Transactions on Circuits and Systems . 1990,第3期

机译：考虑小尺寸CMOS反相器影响的互连线中的信号延迟
3. A reliable CMOS 16:1 binary-tree multiplexer applying delay compensation techniques [J] . Jae-Tack Yoo, Kwansu Shon, Soo-Won Kim IEICE Electronics Express . 2007,第17期

机译：采用延迟补偿技术的可靠CMOS 16：1二叉树多路复用器
4. Accurate speed improvement techniques for RC line and tree interconnections in CMOS VLSI [C] . Chung-Hu Wu, Ming-Chuen Shaiu . 1990

机译：CMOS VLSI中用于RC线和树互连的精确速度改进技术
5. Improvement of a propagation delay model for CMOS digital logic circuits. [D] . Stamness, Rodger Lawrence. 2010

机译：CMOS数字逻辑电路传播延迟模型的改进。
6. Break-before-Make CMOS Inverter for Power-Efficient Delay Implementation [O] . Janez Puhan, Dušan Raič, Tadej Tuma, -1

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7. Modeling of Polysilicide Gate Resistance Effect on Inverter Delay and Power Consumption Using Distributed RC Method and Branching Technique [O] . Y. Koolivand, A. Zahabi, N. Masoumi 2015

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8. Derivation of Delay Insensitive and Speed Independent CMOS Circuits UsingDirected Commands and Production Rule Sets [R] . Koerver, W. 1993

机译：利用导向命令和生产规则集推导延迟不敏感和速度独立的CmOs电路

Delay models and speed improvement techniques for RC tree interconnections among small-geometry CMOS inverters

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