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首页> 外文期刊>IEEE Journal of Solid-State Circuits >Novel design for testability schemes for CMOS ICs
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Novel design for testability schemes for CMOS ICs

机译：CMOS IC可测试性方案的新颖设计

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The authors present ideas for addressing the problem of detecting non-stuck-at faults in CMOS circuits that cannot be revealed by means of conventional methods (i.e., as logical errors in the steady-state response). Two techniques are proposed for detecting analog faults, particularly those resulting in intermediate voltages along circuit branches due to faulty conductive paths between the power supply and ground. Involving the conversion of analog faults into stuck-ats and the use of distributed testing logic, these techniques are shown to avoid the drawbacks of previous solutions. A method is proposed for online detection of delay faults, so far not yet considered in the context of design-for-testability. All the proposed techniques require little extra hardware and lead to minimal performance degradations.
机译：作者提出了解决检测CMOS电路中非卡滞故障的方法的想法，这些问题无法通过常规方法来揭示（即，稳态响应中的逻辑错误）。提出了两种技术来检测模拟故障，特别是由于电源和地之间的导电路径故障而导致沿电路分支产生中间电压的模拟故障。这些技术涉及到将模拟故障转换为固定故障并使用分布式测试逻辑，从而避免了先前解决方案的弊端。提出了一种在线检测延迟故障的方法，到目前为止，在可测试性设计的背景下尚未考虑该方法。所有提出的技术都几乎不需要额外的硬件，并且导致性能降到最低。

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