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首页> 外文期刊>IEEE Journal of Solid-State Circuits >Second-generation RISC floating point with multiply-add fused
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Second-generation RISC floating point with multiply-add fused

机译：第二代RISC浮点，具有乘法加法融合

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摘要

A 440000-transistor second-generation RISC (reduced instruction set computer) floating-point chip is described. The pipeline latency is only two cycles, and a double-precision result is produced every cycle. System throughput and accuracy are increased by using a floating-point multiply-add-fused unit, which carries out a double-precision accumulate as a two-cycle pipelined execution with only one rounding error. While the cycle time (40 ns) is competitive with other CMOS RISC systems, the floating-point performance stretches to the range of bipolar RISC systems (7.4-13 MFLOPS LINPACK). Leading zero anticipation makes the two-cycle pipeline possible by nearly eliminating the additional postnormalization time, and it allows for reduced overall system latency. Partial decode shifters allow complete time sharing for the multiply and data alignment. Improved design techniques for logarithmic addition and higher order counters for multiplication complete this second-generation RISC floating-point unit design.
机译：描述了一种440000晶体管的第二代RISC（精简指令集计算机）浮点芯片。流水线等待时间仅为两个周期，并且每个周期都会产生双精度结果。通过使用浮点乘加融合单元可以提高系统吞吐量和精度，该单元执行双精度累加，作为两个周期的流水线执行，且只有一个舍入误差。尽管周期时间（40 ns）与其他CMOS RISC系统具有竞争优势，但浮点性能可扩展到双极性RISC系统的范围（7.4-13 MFLOPS LINPACK）。领先的零预期几乎消除了额外的归一化后的时间，从而使两个周期的流水线成为可能，并且可以减少总体系统延迟。部分解码移位器可为乘法和数据对齐提供完整的时间共享。对数加法的改进设计技术和乘法的高阶计数器完成了第二代RISC浮点单元设计。

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