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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 78.5-dB SNDR Radiation- and Metastability-Tolerant Two-Step Split SAR ADC Operating Up to 75 MS/s With 24.9-mW Power Consumption in 65-nm CMOS
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A 78.5-dB SNDR Radiation- and Metastability-Tolerant Two-Step Split SAR ADC Operating Up to 75 MS/s With 24.9-mW Power Consumption in 65-nm CMOS

机译：78.5dB SNDR耐辐射和亚稳态的两步分离式SAR ADC，在65nm CMOS中功耗高达24.9mW，工作速率高达75MS / s

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摘要

This paper presents a 14-bit radiation- and metastability-tolerant two-step split successive-approximation register (SAR) analog-to-digital converter (ADC) that achieves a 78.5-dB peak signal-to-noise-and-distortion ratio (SNDR) and a 103-dB peak spurious-free dynamic range (SFDR) at 35 MS/s. The prototype operates up to 75 MS/s with less than 25-mW power consumption. To tolerate errors originating from radiations and/or metastability, multiple redundancy techniques are implemented hierarchically from the system level to the circuit level. At the system level, the deployment of the split architecture plus a few additional error detection techniques not only identify but also correct the errors, leading to a p to p(2) error rate reduction. These detection techniques include a residue over-and under (OU)-flow detection using the second-stage digital codes, an extra bit (EB)-cycle error detection with LSB repeating using a larger digital-to-analog converter (DAC) capacitor, and a parity bit (PB) error detection for on-the-fly SAR data latch protection. Sub-radix-2 DAC and reference voltage scaling also create circuit-level intra-and inter-stage redundancy, further improving the robustness of the conversion process. Preamplifier sharing and offset digital calibration alleviate the offset problem between the residue amplifier (RA) and the first-stage comparator. Two reference buffers are implemented on chip with a 1.8-V supply. Fabricated in a 65-nm CMOS process, the ADC core occupies an active area of 0.342 mm(2).
机译：本文介绍了一种14位耐辐射和亚稳性的两步拆分逐次逼近寄存器（SAR）模数转换器（ADC），其峰值信噪比达到78.5 dB （SNDR）和103 MS / s的103dB峰值无杂散动态范围（SFDR）。该原型的运行速度高达75 MS / s，功耗不到25 mW。为了容忍源自辐射和/或亚稳定性的错误，从系统级别到电路级别逐级实施了多种冗余技术。在系统级别，拆分体系结构的部署以及一些其他的错误检测技术不仅可以识别而且可以纠正错误，从而降低了p到p（2）的错误率。这些检测技术包括使用第二级数字代码的残余物上下流动（OU）检测，使用较大的数模转换器（DAC）电容器的LSB重复的额外位（EB）周期错误检测，以及用于即时SAR数据锁存保护的奇偶校验位（PB）错误检测。 Sub-radix-2 DAC和基准电压定标还创建了电路级级间和级间冗余，从而进一步提高了转换过程的鲁棒性。前置放大器共享和偏移数字校准减轻了残留放大器（RA）与第一级比较器之间的偏移问题。两个参考缓冲器通过1.8V电源在芯片上实现。 ADC内核采用65 nm CMOS工艺制造，其有效面积为0.342 mm（2）。

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