A 56 bit S/370 sign-magnitude adder for floating-point operations implemented in a four-level metal bipolar master-slice technology is described. The design of the two-to-one adder is based on a carry lookahead scheme with implicit calculation of the end-around carry. The implementation of the floating-point adder and the error-detecting logic requires one chip of 7500 automatically placed and wired NAND gates. The chip die size is 7.39*7.39 mm/sup 2/, and it is mounted on a metallized ceramic substrate. The floating-point sign-magnitude adder chip is used in the IBM 9370 Model 60 (9375) engineering scientific accelerator card.
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机译：描述了一种以四级金属双极主切片技术实现的用于浮点运算的56位S / 370符号幅度加法器。二对一加法器的设计基于进位超前方案，并隐式计算了环回进位。浮点加法器和错误检测逻辑的实现需要7500个自动放置和连接的NAND门芯片。芯片裸片尺寸为7.39 * 7.39 mm / sup 2 /，并安装在金属化陶瓷基板上。浮点符号幅度加法器芯片在IBM 9370 Model 60（9375）工程科学加速卡中使用。
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