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A 0.016 mm

机译：0.016毫米

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Ultra-low-power systems, such as wearables and Internet-of-Things (IoT), require power- and volume-efficient micro-controller units (MCUs) capable of operating across a wide range of frequencies under extreme power constraints. This paper presents the techniques to implement clock generators that cater to the needs of such MCUs and other similar ultra-low-power applications. RC relaxation oscillators (RCOs) are shown to achieve excellent frequency stability when generating clocks in kilohertz to megahertz range but are not very power efficient (5 mu W/MHz). Their power efficiency further degrades at higher frequencies because of additional power needed to compensate for the impact of temperature-dependent comparator's delay on frequency stability. On the other hand, ring oscillators (ROs) can generate higher frequency and lower noise clocks more power efficiently but exhibit very poor voltage and temperature sensitivity. In view of these complementary tradeoffs offered by RC oscillator and RO, this paper seeks to combine their advantages by using a phase-locked loop (PLL) to multiply the frequency of an RC oscillator using an RO. A new type-II digital PLL (DPLL) that uses a delay-modulating clock buffer to implement the proportional control and a low-area digital-to-analog converter to implement the digitally controlled oscillator is presented. Fabricated in the 65 nm CMOS process, the prototype PLL generates 50-300 MHz output frequencies from a reference clock in the range of 0.5-5 MHz. The DPLL occupies an active area of 125 mu m x 125 mu m and achieves +/- 0.33% period jitter while consuming 63.5 mu W at an output frequency of 240 MHz. This translates to an excellent power efficiency of 0.26 mu W/MHz at 0.8-V supply voltage.
机译：诸如可穿戴设备和物联网（IoT）之类的超低功耗系统要求具有高功率和体积效率的微控制器单元（MCU），它们必须能够在极端功率限制下在多种频率下工作。本文介绍了实现满足此类MCU和其他类似超低功耗应用需求的时钟发生器的技术。当产生千赫兹至兆赫兹范围的时钟时，RC弛张振荡器（RCO）表现出出色的频率稳定性，但功率效率不高（5μW / MHz）。由于需要额外的功率来补偿温度相关比较器的延迟对频率稳定性的影响，因此它们的功率效率在更高的频率下会进一步降低。另一方面，环形振荡器（RO）可以更有效地产生更高的频率和更低的噪声时钟，但电压和温度灵敏度却很差。鉴于RC振荡器和RO提供的这些互补的折衷，本文试图通过使用锁相环（PLL）乘以RO来放大RC振荡器的频率，从而结合其优势。提出了一种新型的II型数字PLL（DPLL），该数字PLL使用延迟调制时钟缓冲器来实现比例控制，并使用低面积的数模转换器来实现数控振荡器。原型PLL采用65 nm CMOS工艺制造，可从0.5-5 MHz范围内的参考时钟产生50-300 MHz输出频率。 DPLL的有效面积为125μmx 125μm，并实现+/- 0.33％的周期抖动，同时在240 MHz的输出频率下消耗63.5μW。这意味着在0.8V电源电压下具有0.26μW/ MHz的出色功率效率。

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