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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 25-Gb/s, 2.1-pJ/bit, Fully Integrated Optical Receiver With a Baud-Rate Clock and Data Recovery
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A 25-Gb/s, 2.1-pJ/bit, Fully Integrated Optical Receiver With a Baud-Rate Clock and Data Recovery

机译：具有波特率时钟和数据恢复功能的25Gb / s，2.1pJ / bit，全集成光接收机

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摘要

This paper presents the design of a single-chip, 25-Gb/s optical receiver comprising of a front-end amplifier, a clock and data recovery (CDR), and a 1:4 demultiplexer. Incorporating with an integrating-type receiver front end, a new baud-rate CDR is proposed to achieve both high sensitivity and highly energy-efficient operations. Compared to conventional 2x oversampling CDRs that require edge samples for timing adjustment, the baud rate CDR reduces the number of sampling phases by half to save both area and power consumption. In addition, a hybrid loop filter consisting of analog decimation and digital postprocessing is proposed. It greatly relaxes the speed requirement of an all-digital loop filter while keeping the flexibility of a programmable loop bandwidth. By applying a pseudo random bit sequence (PRBS) 231-1 test pattern and using a photo detector whose responsivity is 0.53 A/W, the input sensitivities of the optical receiver at 20 and 25 Gb/s operations are about -13.8 and -8.7 dBm respectively, for a bit error rate (BER) of less than 10(-12). The recovered data jitter at the demultiplexer output is about 1.7-ps rms. The measured jitter tolerance (JTOL) exceeds the mask defined by the IEEE 802.3ba standard. Implemented in a 40-nm CMOS process, the chip area is only 0.09 mm2. The energy efficiency of the entire receiver is 2.1 pJ/bit at 25-Gb/s operation.
机译：本文介绍了一种单芯片25 Gb / s光接收器的设计，该接收器包括一个前端放大器，一个时钟和数据恢复（CDR）以及一个1：4解复用器。结合集成型接收机前端，提出了一种新的波特率CDR，以实现高灵敏度和高能效操作。与需要边缘采样以进行时序调整的常规2x过采样CDR相比，波特率CDR将采样阶段的数量减少了一半，从而节省了面积和功耗。此外，提出了一种由模拟抽取和数字后处理组成的混合环路滤波器。它极大地放宽了全数字环路滤波器的速度要求，同时保持了可编程环路带宽的灵活性。通过应用伪随机比特序列（PRBS）231-1测试图并使用其响应度为0.53 A / W的光电检测器，光接收器在20和25 Gb / s操作下的输入灵敏度约为-13.8和-8.7误码率（BER）小于10（-12）时分别为dBm。在解复用器输出处恢复的数据抖动约为1.7 ps rms。测得的抖动容限（JTOL）超过了IEEE 802.3ba标准定义的掩码。以40纳米CMOS工艺实现，芯片面积仅为0.09平方毫米。在25 Gb / s的工作速率下，整个接收器的能效为2.1 pJ / bit。

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