A GaAs depletion-mode MESFET integrated circuit which is implemented with buffered FET logic and contains 155 gates is described. The chip is composed of a 4-bit adder, a 4-bit register, and lookahead-carry logic capable of connecting up to four chips in a 16-bit parallel adder-accumulator circuit for direct digital synthesis of a sinewave. Fully functional chips have been fabricated by a GaAs foundry. Design rules were conservatively set to 1.5- mu m FET gate lengths. In synchronous operation without clock skew, a 16-bit four-chip configuration was breadboarded and operated at clock frequencies up to 200 MHz. Both a 4-bit one-chip breadboard and an 8-bit two-chip breadboard operated at clock frequencies up to 340 MHz. Chip power dissipation is approximately 500 mW including pad driver circuits. A next-generation pipelined adder-accumulator design based on the experience gained with this chip design is presented. For the LSI pipelined design with 1- mu m gate length, maximum clock speed is projected as 800 MHz to 1 GHz.
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