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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 2.0–5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider
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A 2.0–5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider

机译:具有扩展范围多模分频器的2.0–5.5 GHz宽带基于环的数字小数N PLL

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摘要

Phase noise performance of ring oscillator based digital fractional-N phase-locked loops (FNPLLs) is severely compromised by conflicting bandwidth requirements to simultaneously suppress oscillator phase and quantization noise introduced by the time-to-digital converter (TDC), fractional divider, and digital-to-analog converter (DAC). As a consequence, their figure-of-merit (FoMJ) that quantifies the power–jitter tradeoff is at least 25 dB worse than their LC-oscillator-based FNPLL counterparts. This paper seeks to close this performance gap by extending PLL bandwidth (BW) using quantization noise cancellation techniques and by employing a dual-path digital loop filter to suppress the detrimental impact of DAC quantization noise. Fabricated in 65 nm CMOS process, the proposed FNPLL operates over a wide frequency range of 2.0–5.5 GHz using a modified extended range multi-modulus divider with seamless switching. The proposed digital FNPLL achieves 1.9 psrms integrated jitter while consuming only 4 mW at 5 GHz output. The measured in-band phase noise is better than −96 dBc/Hz at 1 MHz offset. The proposed FNPLL achieves wide BW up to 6 MHz using a 50 MHz reference and its FoMJ is −228.5 dB, which is the best among all reported ring-based FNPLLs.
机译:基于环形振荡器的数字小数N锁相环(FNPLL)的相位噪声性能受到带宽需求冲突的严重影响,以同时抑制由时间数字转换器(TDC),分数分频器和数模转换器(DAC)。结果,量化功率抖动权衡的品质因数(FoMJ)比其基于LC振荡器的FNPLL要差至少25 dB。本文试图通过使用量化噪声消除技术扩展PLL带宽(BW)并采用双路径数字环路滤波器来抑制DAC量化噪声的有害影响,来弥补这一性能差距。拟议的FNPLL采用65 nm CMOS工艺制造,使用改进的扩展范围多模分频器和无缝切换功能,可在2.0–5.5 GHz的宽频率范围内工作。拟议中的数字FNPLL实现了1.9 psrms的集成抖动,同时在5 GHz输出下仅消耗4 mW。在1 MHz偏移下测得的带内相位噪声优于-96 dBc / Hz。拟议的FNPLL使用50 MHz基准可实现高达6 MHz的宽带宽,其FoMJ为−228.5 dB,在所有已报道的基于环的FNPLL中是最好的。

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