A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers

Lilan Yu; Masaya Miyahara; Akira Matsuzawa

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A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers

机译：使用线性化开环放大器的9位1.8 GS / s 44 mW流水线ADC

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摘要

This paper presents a 9-bit 1.8 GS/s pipelined analog-to-digital converter (ADC) using open-loop amplifiers. In this ADC, open-loop amplifiers are used as residue amplifiers to increase the sampling rate of the ADC with relatively low power consumption. A linearization technique is proposed to suppress the SNDR decrease caused by the nonlinearity of open-loop amplifiers. The attenuation in the capacitor digital-to-analog converter (CDAC) is utilized to calibrate the gain error of the pipelined stages. In addition, top-plate sampling is proposed to further enhance the power efficiency of the residue amplifiers. With these techniques, the ADC achieves a high sampling rate and high power efficiency. A prototype of the ADC is fabricated in 65 nm CMOS technology. An SNDR of 47 dB and a FoM of 134 fJ/conversion-step is achieved at a sampling rate of 1.8 GS/s with 900 MHz input, while consuming 44 mW from a 1.2 V supply.

机译：本文提出了一种使用开环放大器的9位1.8 GS / s流水线模数转换器（ADC）。在此ADC中，开环放大器用作残差放大器，以相对较低的功耗提高ADC的采样率。提出了一种线性化技术来抑制由开环放大器的非线性引起的SNDR降低。电容器数模转换器（CDAC）中的衰减用于校准流水线级的增益误差。另外，提出了顶板采样以进一步提高残留放大器的功率效率。利用这些技术，ADC实现了高采样率和高功率效率。 ADC的原型采用65 nm CMOS技术制造。输入为900 MHz时，采样率为1.8 GS / s，实现SNDR为47 dB，FoM为134 fJ /转换步长，而1.2 V电源消耗44 mW的功率。

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来源
《IEEE Journal of Solid-State Circuits》 |2016年第10期|2210-2221|共12页
作者
Lilan Yu; Masaya Miyahara; Akira Matsuzawa;
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作者单位

Department of Physical Electronics, Tokyo Institute of Technology, Tokyo, Japan;

Department of Physical Electronics, Tokyo Institute of Technology, Tokyo, Japan;

Department of Physical Electronics, Tokyo Institute of Technology, Tokyo, Japan;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类
关键词
Linearity; Power demand; Gain; Bandwidth; Calibration; Linearization techniques; Signal resolution;

机译：线性;功率需求;增益;带宽;校准;线性化技术;信号分辨率;

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1. A 1-GS/s 9-bit Zero-Crossing-Based Pipeline ADC Using a Resistor as a Current Source [J] . Young-Hwa Kim, SeongHwan Cho IEEE transactions on very large scale integration (VLSI) systems . 2016,第7期

机译：使用电阻器作为电流源的1-GS / s 9位基于零交叉的流水线ADC
2. Design of Interpolated Pipeline ADC Using Low-Gain Open-Loop Amplifiers [J] . Hyunui LEE, Masaya MIYAHARA, Akira MATSUZAWA IEICE Transactions on Electronics . 2013,第6期

机译：使用低增益开环放大器的内插流水线ADC设计
3. A 4-GS/s 11.3-mW 7-bit Time-Based ADC With Folding Voltage-to-Time Converter and Pipelined TDC in 65-nm CMOS [J] . Yi Il-Min, Miura Naoki, Nosaka Hideyuki IEEE Journal of Solid-State Circuits . 2021,第2期

机译：基于4GS / s 11.3-MW 7位时间的ADC，具有折叠电压与时转换器和65-NM CMOS的流水线TDC
4. A 9-bit 1.8-GS/s pipelined ADC using linearized open-loop amplifiers [C] . Lilan Yu, Masaya Miyahara, Akira Matsuzawa IEEE Asian Solid State Circuits Conference . 2015

机译：使用线性化开环放大器的9位1.8-GS / s流水线ADC
5. A Single-channel High-speed Pipelined-SAR ADC with an Open-loop MDAC [D] . Wu, Chao. 2018

机译：单通道高速流水线-SAR ADC，具有开环MDAC
6. Low-power 6-bit 1-GS/s two-channel pipeline ADC with open-loop amplification using amplifiers with local-feedback [O] . A. Galhardo, J. Goes, N. Paulino 2008

机译：低功耗6位1-GS / S双通道管道ADC，采用具有本地反馈的放大器的开环放大

A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers

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