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首页> 外文期刊>Solid-State Circuits, IEEE Journal of >A 1 × 400 Backside-Illuminated SPAD Sensor With 49.7 ps Resolution, 30 pJ/Sample TDCs Fabricated in 3D CMOS Technology for Near-Infrared Optical Tomography
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A 1 × 400 Backside-Illuminated SPAD Sensor With 49.7 ps Resolution, 30 pJ/Sample TDCs Fabricated in 3D CMOS Technology for Near-Infrared Optical Tomography

机译：采用3D CMOS技术制造的具有49.7 ps分辨率，30 pJ /采样TDC的1×400背面照明SPAD传感器，用于近红外光学层析成像

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摘要

A 1 × 400 array of backside-illuminated SPADs fabricated in 130 nm 3D IC CMOS technology is presented. Sensing is performed in the top tier substrate and time-to-digital conversion in the bottom tier. Clusters of eight pixels are connected to a winner-take-all circuit with collision detection capabilities to realise an efficient sharing of the time-to-digital converter (TDC). The sensor's 100 TDCs are based on a dual-frequency architecture enabling 30 pJ per conversion at a rate of 13.3 ms/s per TDC. The resolution (1 LSB) of the TDCs is 49.7 ps with a standard deviation of 0.8 ps across the entire array; the mean DNL is ±0.44 LSB and the mean INL is ±0.47. The chip was designed for use in near-infrared optical tomography (NIROT) systems for brain imaging and diagnostics. Measurements performed on a silicon phantom proved its suitability for NIROT applications.
机译：展示了采用130 nm 3D IC CMOS技术制造的1×400背面照明的SPAD阵列。传感在顶层基板中进行，而时间数字转换则在底层中进行。八个像素的群集连接到具有碰撞检测功能的中奖者通吃电路，以实现时间数字转换器（TDC）的有效共享。传感器的100个TDC基于双频架构，使每个转换30 pJ的速率为每个TDC 13.3 ms / s。 TDC的分辨率（1 LSB）为49.7 ps，整个阵列的标准偏差为0.8 ps。平均DNL为±0.44 LSB，平均INL为±0.47。该芯片设计用于近红外光学断层扫描（NIROT）系统，用于大脑成像和诊断。在硅模型上进行的测量证明了其适用于NIROT应用。

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