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首页> 外文期刊>IEEE Journal of Solid-State Circuits >Absolute Value, 1% Linear and Lossless Current-Sensing Circuit for the Step-Down DC-DC Converters With Integrated Power Stage
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Absolute Value, 1% Linear and Lossless Current-Sensing Circuit for the Step-Down DC-DC Converters With Integrated Power Stage

机译：具有集成功率级的降压型DC-DC转换器的绝对值，1％线性无损电流检测电路

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摘要

A circuit allowing to accurately measure the average output current of the step-down DC-DC converter operating in PWM mode is presented. It relies on the measurement of the average voltage drop across the PMOS-NMOS or dual-NMOS power stage. The average voltage drop is measured by a simple RC filter, as a difference between the power-stage average output voltage and the average output voltage of an auxiliary “ideal” power stage. Obtained voltage drop is applied to an element labeled as “composite load”. This approach allows to remove the dominant errors originating from the use of a standard sense-FET circuit. Obtained output current image exhibits very low linearity error <1% in 10 mA to 2.1 A range, and high ±4% accuracy of the conversion gain over supply voltage, temperature and statistical chip-by-chip variations. The performances of integrated current sensor are demonstrated by measurements on 3.2 MHz step down DC-DC converter integrated in 0.5 µm CMOS process.
机译：提出了一种电路，该电路可以精确测量以PWM模式工作的降压型DC-DC转换器的平均输出电流。它依赖于PMOS-NMOS或双NMOS功率级上平均电压降的测量。平均电压降由一个简单的RC滤波器测量，作为功率级平均输出电压和辅助“理想”功率级的平均输出电压之间的差。将获得的电压降施加到标为“复合负载”的元件上。这种方法可以消除源于使用标准Sense-FET电路的主要误差。所获得的输出电流图像在10 mA至2.1 A的范围内表现出非常低的线性误差<1％，并且在电源电压，温度和逐芯片统计变化范围内，转换增益的精度高达±4％。集成电流传感器的性能通过在集成于0.5 µm CMOS工艺中的3.2 MHz降压DC-DC转换器上的测量得到证明。

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