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Analysis of Metastability in Pipelined ADCs

机译:流水线ADC的亚稳定性分析

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摘要

A critical issue in the design of high-speed ADCs relates to the errors that result from comparator metastability. Studied for flash architectures in the past, this phenomenon assumes new dimensions in pipelined converters, creating far more complex error mechanisms. This paper presents a comprehensive analysis of comparator metastability effects in pipelined ADCs and develops a method to predict the error behavior for a given input signal PDF Different error mechanisms are identified and formulated to obtain the probability of error versus the magnitude of error. An 8-bit 600 MS/s ADC fabricated in 65 nm CMOS technology has been used to assess the validity of the analytical results.
机译:高速ADC设计中的一个关键问题与比较器亚稳性引起的误差有关。过去曾针对闪存架构进行过研究,这种现象在流水线式转换器中采用了新的维度,从而产生了更为复杂的错误机制。本文对流水线ADC中比较器的亚稳态效应进行了全面分析,并开发了一种方法来预测给定输入信号PDF的误差行为。识别并制定了不同的误差机制,以得出误差概率与误差幅度的关系。采用65 nm CMOS技术制造的8位600 MS / s ADC已用于评估分析结果的有效性。

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