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首页> 外文期刊>IEEE Journal of Solid-State Circuits >An Energy Efficient Full-Frame Feature Extraction Accelerator With Shift-Latch FIFO in 28 nm CMOS
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An Energy Efficient Full-Frame Feature Extraction Accelerator With Shift-Latch FIFO in 28 nm CMOS

机译:具有28 nm CMOS移位锁存FIFO的高效节能全帧特征提取加速器

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This paper presents an energy-efficient feature extraction accelerator design aimed at visual navigation. The hardware-oriented algorithmic modifications such as a circular-shaped sampling region and unified description are proposed to minimize area and energy consumption while maintaining feature extraction quality. A matched-throughput accelerator employs fully-unrolled filters and single-stream descriptor enabled by algorithm-architecture co-optimization, which requires lower clock frequency for the given throughput requirement and reduces hardware cost of description processing elements. Due to the large number of FIFO blocks, a robust low-power FIFO architecture for the ultra-low voltage (ULV) regime is also proposed. This approach leverages shift-latch delay elements and balanced-leakage readout technique to achieve 62% energy savings and 37% delay reduction. We apply these techniques to a feature extraction accelerator that can process 30 fps VGA video in real time and is fabricated in 28 nm LP CMOS technology. The design consumes 2.7 mW with a clock frequency of 27 MHz at ${rm V} _{rm dd} = $ 470 mV, providing 3.5× better energy efficiency than previous state-of-the-art while extracting features from entire image.
机译:本文提出了一种针对视觉导航的节能特征提取加速器设计。提出了诸如圆形采样区域和统一描述之类的面向硬件的算法修改,以在保持特征提取质量的同时最小化面积和能耗。匹配吞吐量的加速器采用完全展开的滤波器和通过算法-架构共同优化实现的单流描述符,对于给定的吞吐量要求,它需要较低的时钟频率,并减少了描述处理元素的硬件成本。由于先进先出(FIFO)块数量众多,因此还提出了用于超低电压(ULV)机制的稳健的低功耗FIFO体系结构。这种方法利用了移位锁存延迟元件和平衡泄漏读出技术,可节省62%的能源并减少37%的延迟。我们将这些技术应用于可以实时处理30 fps VGA视频并以28 nm LP CMOS技术制造的特征提取加速器。该设计功耗为2.7 mW,时钟频率为27 MHz($ {rm V} _ {rm dd} = $ 470 mV),在从整个图像中提取特征的同时,其能效比以前的先进技术高3.5倍。

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