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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 0.5-to-3 GHz Software-Defined Radio Receiver Using Discrete-Time RF Signal Processing
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A 0.5-to-3 GHz Software-Defined Radio Receiver Using Discrete-Time RF Signal Processing

机译:使用离散射频信号处理的0.5至3 GHz软件定义无线电接收机

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摘要

A software-defined radio (SDR) wireless receiver leveraging discrete-time (DT) RF signal processing is introduced. The proposed DT signal processor, which applies switched capacitor techniques to radio frequencies, achieves harmonic rejection, image rejection, and frequency translation simultaneously. A frequency tunable high-Q 2nd-order bandpass input impedance is synthesized by the DT RF signal processor, which enhances the front-end interference rejection and frequency selectivity. A proof-of-concept SDR receiver prototype, including a 65 nm LP CMOS chip and a custom designed board, is presented. The highly programmable chip allows independent control of individual block parameters and bias operating points for optimum performance under various signal scenarios. The 0.5-to-3 GHz SDR receiver achieves out-of-band IIP3 > 11 dBm, IIP2 > 46 dBm, uncalibrated 3rd and 5th order harmonic rejection exceeding 46 dB and 51 dB, respectively, and can handle up to $-$5 dBm blockers with less than 5 dB degradation in signal-to-noise ratio (SNR) when the blocker offset frequency is 10 times the signal bandwidth irrespective of the center frequency.
机译:引入了利用离散时间(DT)RF信号处理的软件定义无线电(SDR)无线接收器。提议的DT信号处理器将开关电容器技术应用于射频,同时实现了谐波抑制,镜像抑制和频率转换。 DT RF信号处理器合成了频率可调的高Q 2阶带通输入阻抗,从而增强了前端干扰抑制能力和频率选择性。提出了概念验证的SDR接收器原型,其中包括65 nm LP CMOS芯片和定制设计的板。高度可编程的芯片允许独立控制各个模块参数和偏置工作点,以在各种信号情况下实现最佳性能。 0.5至3 GHz SDR接收机的带外IIP3> 11 dBm,IIP2> 46 dBm,未经校准的三阶和五阶谐波抑制分别超过46 dB和51 dB,并且可以处理高达$-$ 5 dBm当阻塞器偏移频率是信号带宽的10倍时,无论中心频率如何,信噪比(SNR)降级小于5 dB的阻塞器。

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