Analysis and Design of a Power-Scalable Continuous-Time FIR Equalizer for 10 Gb/s to 25 Gb/s Multi-Mode Fiber EDC in 28 nm LP CMOS

Mammei E.; Loi F.; Radice F.; Dati A.; Bruccoleri M.; Bassi M.; Mazzanti A.

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Analysis and Design of a Power-Scalable Continuous-Time FIR Equalizer for 10 Gb/s to 25 Gb/s Multi-Mode Fiber EDC in 28 nm LP CMOS

机译：用于28纳米LP CMOS的10 Gb / s至25 Gb / s多模光纤EDC的功率可扩展连续时间FIR均衡器的分析和设计

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A continuous-time 7-tap FIR equalizer tailored to dispersion compensation in multi-mode fiber links is presented. By using a novel active delay line, the ultra-compact equalizer is very flexible, maintaining optimal performances and power scalability over a wide range of input data-rates. Particular care is taken to address critical issues of continuous-time realizations, such as noise, linearity and dynamic range. All-pass stages, realized with a simple circuit topology featuring high linearity and wide bandwidth, are investigated to implement the active delay line elements. Filter tap coefficients are realized with programmable transconductors and output currents are summed through a transimpedance amplifier, providing simultaneously high gain and wide bandwidth. Extensive experimental results, carried out on test chips realized in 28 nm LP CMOS technology, are presented. The equalizer demonstrates successful operation with variable data-rates ranging from 10 Gb/s to 25 Gb/s and power dissipation scalable from 55 mW to 90 mW. Compared to previously reported high-speed FIR equalizers, the proposed solution accepts the largest variation of the input data-rate with state-of-the-art power efficiency and core silicon area of only 0.085 mm, meeting the demand of emerging 400 Gb/s standards.

机译：提出了一种专为多模光纤链路中的色散补偿而设计的连续时间7抽头FIR均衡器。通过使用新颖的有源延迟线，超紧凑型均衡器非常灵活，可在各种输入数据速率范围内保持最佳性能和功率可扩展性。要特别注意解决连续时间实现的关键问题，例如噪声，线性和动态范围。研究了通过具有高线性度和宽带宽的简单电路拓扑实现的全通级，以实现有源延迟线元件。滤波器抽头系数通过可编程跨导电路实现，输出电流通过跨阻放大器求和，同时提供高增益和宽带宽。给出了在以28 nm LP CMOS技术实现的测试芯片上进行的大量实验结果。均衡器演示了成功的操作，其可变数据速率范围为10 Gb / s至25 Gb / s，功耗可扩展至55 mW至90 mW。与先前报道的高速FIR均衡器相比，该解决方案以最大的功率效率和仅0.085 mm的核心硅面积接受了输入数据速率的最大变化，满足了新兴的400 Gb / s的需求。的标准。

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来源
《Solid-State Circuits, IEEE Journal of》 |2014年第12期|3130-3140|共11页
作者
Mammei E.; Loi F.; Radice F.; Dati A.; Bruccoleri M.; Bassi M.; Mazzanti A.;
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作者单位

Universit?? degli Studi di Pavia, Pavia, Italy;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类
关键词
CMOS integrated circuits; Delay lines; Delays; Equalizers; Finite impulse response filters; Gain; Noise; 28 nm CMOS; FIR equalizer; all-pass; delay line; electronic dispersion compensation; multi-mode fiber;

机译：CMOS集成电路;延迟线;延迟;均衡器;有限脉冲响应滤波器;增益;噪声;28 nm CMOS;FIR均衡器;全通;延迟线;电子色散补偿;多模光纤;

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1. Multi-level pre-equalization using binary analog FIR filters based on 28-nm FD-SOI for 20-Gb/s 4-PAM multi-mode fiber transmission [J] . Ryoichiro Nakamura, Kenta Amino, Kawori Sekine, IEICE Communications Express . 2017,第4期

机译：使用基于28 nm FD-SOI的二进制模拟FIR滤波器进行多级预均衡，以实现20 Gb / s 4-PAM多模光纤传输
2. A 0.13-Μm CMOS 5-Gb/s 10-m 28AWG cable transceiver with no-feedback-loop continuous-time post-equalizer [J] . Kudoh Y., Fukaishi M., Mizuno M. IEEE Journal of Solid-State Circuits . 2003,第5期

机译：具有无反馈环路连续时间后置均衡器的0.13μmCMOS 5-Gb / s 10-m 28AWG电缆收发器
3. A 0.13-/spl mu/m CMOS 5-Gb/s 10-m 28AWG cable transceiver with no-feedback-loop continuous-time post-equalizer [J] . Kudoh Y., Fukaishi M., Mizuno M. IEEE Journal of Solid-State Circuits . 2003,第5期

机译：一个0.13 / spl mu / m CMOS 5-Gb / s 10-m 28AWG电缆收发器，具有无反馈环路连续时间后均衡器
4. 8.3 A power-scalable 7-tap FIR equalizer with tunable active delay line for 10-to-25Gb/s multi-mode fiber EDC in 28nm LP-CMOS [C] . Mammei Enrico, Loi Fabrizio, Radice Francesco, IEEE International Solid-State Circuits Conference . 2014

机译：8.3功率可调的7抽头FIR均衡器，带有可调有源延迟线，用于28nm LP-CMOS中的10至25Gb / s多模光纤EDC
5. A novel analog decision-feedback equalizer in CMOS for serial 10-Gb/sec data transmission systems. [D] . Chandramouli, Soumya. 2007

机译：用于串行10 Gb /秒数据传输系统的CMOS中新颖的模拟判决反馈均衡器。
6. Comparative genomic analysis of Lactobacillus plantarum GB-LP4 and identification of evolutionarily divergent genes in high-osmolarity environment [O] . Jaehoon Jung, Kwondo Kim, DongAhn Yoo, -1

机译：植物菌乳GB-LP4的比较基因组分析和高渗环境下进化趋异基因的鉴定
7. Multi-level pre-equalization using binary analog FIR filters based on 28-nm FD-SOI for 20-Gb/s 4-PAM multi-mode fiber transmission [O] . Ryoichiro Nakamura, Kenta Amino, Kawori Sekine, 2017

机译：基于28-NM FD-SOI的二进制模拟FIR滤波器的多级预均衡为20-GB / S 4-PAM多模光纤传输

Analysis and Design of a Power-Scalable Continuous-Time FIR Equalizer for 10 Gb/s to 25 Gb/s Multi-Mode Fiber EDC in 28 nm LP CMOS

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