...
  • 主题
高级搜索  >
历史搜索 清空历史
首页> 外文期刊>Solid-State Circuits, IEEE Journal of >A 3 Megapixel 100 Fps 2.8 src='/images/tex/241.gif' alt='mu'> m Pixel Pitch CMOS Image Sensor Layer With Built-in Self-Test for 3D Integrated Imagers
【24h】

A 3 Megapixel 100 Fps 2.8 src='/images/tex/241.gif' alt='mu'> m Pixel Pitch CMOS Image Sensor Layer With Built-in Self-Test for 3D Integrated Imagers

机译：具有内置自我功能的3兆像素100 Fps 2.8 src =“ / images / tex / 241.gif” alt =“ mu”> m像素间距CMOS图像传感器层-3D集成成像仪测试

获取原文
获取原文并翻译 | 示例
   

获取外文期刊封面封底 >>

       
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

This paper presents a 3 megapixel 100 fps 2.8 $mu$m pixel pitch CMOS image sensor (CIS) layer with built-in self-test (BIST) for three-dimensional (3D) integrated imagers. A modular CIS sub-array is proposed with new readout and control scheme. It needs only one micro-bump ($mu hbox{bump}$) per sub-array, instead of per-pixel or per-column, to release the design rule restriction of the 3D stacking process. The proposed readout structure with in-pixel two-dimensional (2D) decoding function achieves high spatial resolution, without degrading the frame rate. A BIST circuit is also proposed to filter out unqualified CIS layer before chip stacking, improving the yield performance of the final 3D integrated imagers, without adding extra transistor in the pixel. A CIS chip with 16 $,times,$8 sub-arrays and a pixel size of 2.8$,times,$ 2.8 $mu{hbox{m}}^{2}$ was fabricated in TSMC 0.18 $mu{hbox{m}}$ CIS process. The experimental results demonstrate the successful parallel output images of 3 megapixels with 16$,times,$ 8 modules at 100 fps. This shows that the imaging resolution is expandable by the proposed modular sub-array design and is expected to achieve 100 fps at multi-mega imaging for high-speed HDTV camera applications.
机译：本文提出了一种3百万像素，100 fps 2.8微米像素间距CMOS图像传感器（CIS）层，该层具有用于3D（3D）集成成像器的内置自检（BIST）。提出了具有新的读出和控制方案的模块化CIS子阵列。每个子阵列只需要一个微凸点（$ mu hbox {bump} $），而不是每个像素或每个列，就可以释放3D堆叠过程的设计规则限制。所提出的具有像素内二维（2D）解码功能的读出结构可实现高空间分辨率，而不会降低帧速率。还提出了BIST电路，以在芯片堆叠之前滤除不合格的CIS层，从而提高了最终3D集成成像器的良率性能，而无需在像素中添加额外的晶体管。在TSMC 0.18 $ mu {hbox {m}中制造了一个CIS芯片，该芯片具有16个$ times $ 8子阵列和2.8 $ times $ 2.8像素大小的像素。$ mu {hbox {m}} ^ {2} $ } $ CIS流程。实验结果表明，在100 fps下，具有16倍，8倍模块的3百万像素成功并行输出图像。这表明成像分辨率可通过建议的模块化子阵列设计扩展，并有望在高速HDTV摄像机应用的多兆成像中达到100 fps。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号