...
  • 主题
高级搜索  >
历史搜索 清空历史
首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 2-Bit, 24 dBm, Millimeter-Wave SOI CMOS Power-DAC Cell for Watt-Level High-Efficiency, Fully Digital m-ary QAM Transmitters
【24h】

A 2-Bit, 24 dBm, Millimeter-Wave SOI CMOS Power-DAC Cell for Watt-Level High-Efficiency, Fully Digital m-ary QAM Transmitters

机译：2位，24 dBm毫米波SOI CMOS功率DAC单元，用于瓦特级高效全数字mary QAM发送器

获取原文
获取原文并翻译 | 示例
           
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

A high-efficiency, large output-power, mm-wave digital transmitter architecture is proposed for high data rate m-ary QAM transmission. Because it operates entirely in digital mode, without any matching networks, it is scalable in frequency up to at least 50 GHz and portable to future generations of CMOS technologies. It consists of n broadband mm-wave IQ power-DAC pairs directly modulated in amplitude and phase by 4 x n independent digital data streams. The output signals combine in free space to form a programmable ASK, BPSK, QPSK, and m-ary QAM mm-wave transmitter. Several proof-of-concept circuits with one DAC cell, and with one and two IQ pairs of DAC cells were fabricated in 45-nm SOI CMOS. Using a series-stacked differential output stage with four cascoded n-MOSFETs driven in saturation by a CMOS-inverter chain, each power-DAC cell demonstrates a 24.3 dBm output power with 21.3% drain efficiency and 14.6% PAE, at 45 GHz directly into 50-Ω loads. The peak drain efficiency is 30% at 22.5 dBm output power and 19.4% PAE. Experiments show 5-Gb/s BPSK, and simultaneous 2-Gb/s BPSK and 2-Gb/s ASK modulation per DAC cell in the 44-48 GHz range. Eye diagrams at 28 Gb/s further demonstrate the broadband operation of the DAC cell and its suitability as a large-swing NRZ modulator driver in fiberoptic links.
机译：提出了一种高效率，大输出功率的毫米波数字发射机架构，用于高数据速率的玛丽QAM传输。由于它完全在数字模式下运行，没有任何匹配的网络，因此它的频率至少可扩展到50 GHz，并且可移植到下一代CMOS技术。它包含n个宽带毫米波IQ IQ功率DAC对，它们直接由4 x n个独立的数字数据流进行幅度和相位调制。输出信号在自由空间中合并以形成可编程的ASK，BPSK，QPSK和m进制QAM毫米波发射机。在45纳米SOI CMOS中制造了几个具有一个DAC单元以及一对和两对IQ的DAC单元的概念验证电路。使用串联堆叠的差分输出级和四个由CMOS反相器链饱和驱动的级联n-MOSFET时，每个功率DAC单元在45 GHz频率下直接显示24.3 dBm输出功率，21.3％的漏极效率和14.6％的PAE。 50Ω负载。在22.5 dBm输出功率和19.4％PAE时，峰值漏极效率为30％。实验表明，在44-48 GHz范围内，每个DAC单元同时具有5 Gb / s BPSK和同时2 Gb / s BPSK和2 Gb / s ASK调制。 28 Gb / s的眼图进一步说明了DAC单元的宽带工作及其在光纤链路中作为大摆幅NRZ调制器驱动器的适用性。

著录项

相似文献

  • 外文文献
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号