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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A Programmable Calibration/BIST Engine for RF and Analog Blocks in SoCs Integrated in a 32 nm CMOS WiFi Transceiver
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A Programmable Calibration/BIST Engine for RF and Analog Blocks in SoCs Integrated in a 32 nm CMOS WiFi Transceiver

机译：集成在32 nm CMOS WiFi收发器中的SoC中的RF和模拟模块的可编程校准/ BIST引擎

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摘要

This paper presents a flexible and portable digital framework for Built-in Self-Test (BIST) and calibration of RF/analog circuitry. Novel to the proposed testing framework, is a reusable, flexible, drop-in IP core, composed of a centralized custom processing engine with data path, memory architecture and instruction set optimized for efficient execution of compute intensive test and calibration algorithms. The innovative BIST engine is complemented with a calibration and test sequencing methodology exploiting the embedded test hardware, to dynamically correct for transceiver imbalances and non-idealities, as well as to estimate performance parameters such as Error Vector Magnitude (EVM). The engine has been integrated with a WiFi transceiver in a 32 nm SoC test chip to demonstrate the functionality of this framework. This implementation covers an area of 0.63 mm${^2}$ and provides similar performance (e.g., improvements up to 10 dB in EVM for Rx IQ imbalance compensation) to off-chip testing without relying on expensive equipment.
机译：本文提出了一种灵活的便携式数字框架，用于内置自测（BIST）和RF /模拟电路的校准。所提出的测试框架的新颖之处在于，它是一个可重用，灵活的嵌入式IP核，由具有数据路径，内存架构和指令集的集中式定制处理引擎组成，这些引擎针对有效执行计算密集型测试和校准算法进行了优化。创新的BIST引擎通过利用嵌入式测试硬件的校准和测试排序方法进行了补充，可以动态校正收发器的不平衡和不理想情况，并可以估算诸如误差矢量幅度（EVM）之类的性能参数。该引擎已与WiFi收发器集成在32 nm SoC测试芯片中，以演示此框架的功能。此实现覆盖0.63毫米的区域 $ {^ 2} $ 并提供类似的性能（例如，改进幅度高达10 dB在EVM中进行Rx IQ不平衡补偿）到片外测试，而无需依赖昂贵的设备。

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