A Near-Threshold 480 MHz 78 µW All-Digital PLL With a Bootstrapped DCO

Ho Y.; Yang Y.-S.; Chang C.; Su C.

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A Near-Threshold 480 MHz 78 µW All-Digital PLL With a Bootstrapped DCO

机译：具有自举DCO的近阈值480 MHz 78 µW全数字PLL

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摘要

This paper presents a near-threshold low-power all-digital PLL (ADPLL). It includes a 9-bit bootstrapped DCO (BDCO) to reduce supply voltage and power consumption, a weighted thermometer-controlled resistor network (WTRN) to achieve high linearity, and a 4-bit sigma-delta modulator to improve the resolution through dithering. The ADPLL is fabricated in a 90 nm SPRVT low-K CMOS process with a core area of 0.057 mm². The measured results demonstrate that the bootstrapped ring oscillator (BTRO) oscillates at 602 MHz under a supply of 0.5 V and consumes 49.1 µW. The ADPLL operates at 480 MHz (48 MHz) with a power consumption of 78 µW (2.4 µW) under a supply voltage of 0.5 V (0.25 V).

机译：本文提出了一种近阈值低功耗全数字PLL（ADPLL）。它包括一个用于降低电源电压和功耗的9位自举DCO（BDCO），一个用于实现高线性度的加权温度计控制电阻器网络（WTRN），以及一个用于通过抖动提高分辨率的4位sigma-delta调制器。 ADPLL采用90 nm SPRVT低K CMOS工艺制造，核心面积为0.057mm²。测量结果表明，自举环形振荡器（BTRO）在0.5 V的电源下以602 MHz的频率振荡，功耗为49.1 µW。在0.5 V（0.25 V）的电源电压下，ADPLL的工作频率为480 MHz（48 MHz），功耗为78 µW（2.4 µW）。

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来源
《IEEE Journal of Solid-State Circuits》 |2013年第11期|2805-2814|共10页
作者
Ho Y.; Yang Y.-S.; Chang C.; Su C.;
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作者单位

Electrical Engineering Department and Institute of Electrical Control Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C.|c|;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类
关键词
All-digital phase-locked loop (ADPLL); bootstrapped circuit; energy-efficient design; low-power; low-voltage; near-threshold circuit;

机译：全数字锁相环（ADPLL）;自举电路;节能设计;低功耗;低压;近阈值电路;

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1. Near-threshold all-digital PLL with dynamic voltage scaling power management [J] . Chang C.-W., Chang K.-Y., Chu Y.-H., Electronics Letters . 2016,第2期

机译：具有动态电压定标电源管理的近阈值全数字PLL
2. A PVT Tolerant 10 to 500 MHz All-Digital Phase-Locked Loop With Coupled TDC and DCO [J] . Liu W., Li W. (R.), Ren P., Solid-State Circuits, IEEE Journal of . 2010,第2期

机译：具有TDC和DCO耦合的PVT容差10至500 MHz全数字锁相环
3. An all-digital phase-locked loop with a PGTA-based TDC and a 0.6-V DCO [J] . Zixuan Wang, Hao Ding, Hao Xu, IEICE Electronics Express . 2018,第22期

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4. A near-threshold all-digital PLL with a bootstrapped DCO using low-dropout regulator for mitigating PVT-variations [C] . Sangsu Lee, Jaehun Jun, Chulwoo Kim International SoC Design Conference . 2017

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5. A Bang-Bang All-Digital PLL for Frequency Synthesis [D] . Zazzera, Joshua 2012

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6. Multi-gigahertz femtosecond Airy beam optical parametric oscillator pumped at 78 MHz [O] . A. Aadhi, Varun Sharma, N. Apurv Chaitanya, -1

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A Near-Threshold 480 MHz 78 µW All-Digital PLL With a Bootstrapped DCO

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