A 12-Bit 31.1-<inline-formula> <tex-math notation='LaTeX'>$mu$ </tex-math></inline-formula>W 1-MS/s SAR ADC With On-Chip Input-Signal-Independent Calibration Achieving 100.4-dB SFDR Using 256-fF Sampling Capacitance

Shen Junhua; Shikata Akira; Liu Anping; Chen Baozhen; Chalifoux Frederick

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$mu$

W 1-MS/s SAR ADC With On-Chip Input-Signal-Independent Calibration Achieving 100.4-dB SFDR Using 256-fF Sampling Capacitance

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A 12-Bit 31.1- $mu$ W 1-MS/s SAR ADC With On-Chip Input-Signal-Independent Calibration Achieving 100.4-dB SFDR Using 256-fF Sampling Capacitance

机译：一个12位31.1- <内联公式> $ mu $ w 1-ms / s sar adc，带片上输入 - 使用256-FF采样电容实现100.4 dB SFDR的 - 独立校准

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摘要

A 12-bit 31.1-mu W 1-MS/s successive approximation register analog-to-digital converter (ADC) with on-chip input-signal-independent calibration achieving 100.4-dB spurious-free dynamic range is presented. The proposed calibration overcomes the drawbacks of the conventional split-ADC calibration while maintaining fast convergence. The calibration only needs one ADC and is input signal independent. Three techniques are proposed to help achieve this, including shuffling of mismatched MSB capacitors, MSB-LSB swapping, and partial MSB unit-capacitor dithering. In addition, partial bit trial and split-bottom switching circuit techniques are proposed. Silicon results fully validated the design and show 16-bit linearity with only 256-fF sampling capacitance.

机译：提供了12位31.1-MU W 1-MS / S连续近似寄存器模数转换器（ADC），具有片上输入 - 信号独立校准，实现了100.4dB无杂散动态范围。所提出的校准克服了传统的分流ADC校准的缺点，同时保持快速收敛。校准仅需要一个ADC，并且输入信号无关。提出了三种技术来帮助实现这一点，包括混搭错配的MSB电容器，MSB-LSB交换和局部MSB单元电容器抖动。此外，提出了局部比特试验和分离底部开关电路技术。硅结果完全验证了设计，并显示了仅具有256-FF采样电容的16位线性度。

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来源
《IEEE Journal of Solid-State Circuits》 |2019年第4期|937-947|共11页
作者
Shen Junhua; Shikata Akira; Liu Anping; Chen Baozhen; Chalifoux Frederick;
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作者单位

Analog Devices Inc Wilmington MA 01887 USA;

Analog Devices Inc Wilmington MA 01887 USA;

Analog Devices Inc Wilmington MA 01887 USA;

Analog Devices Inc Wilmington MA 01887 USA;

Analog Devices Inc Wilmington MA 01887 USA;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类
关键词
Fast-converging calibration; input-signal-independent calibration; partial bit trial; precision analog-to-digital converter (ADC); small input capacitance; split-bottom switching; successive approximation register (SAR) ADC; ultra-low power (ULP) ADC;

机译：快速融合校准;输入信号无关校准;部分位试验;精确的模数转换器（ADC）;小输入电容;分离底部切换;连续近似寄存器（SAR）ADC;超低功耗（ULP ）ADC;

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专利

1. A 12-Bit 31.1- $mu$ W 1-MS/s SAR ADC With On-Chip Input-Signal-Independent Calibration Achieving 100.4-dB SFDR Using 256-fF Sampling Capacitance [J] . Shen Junhua, Shikata Akira, Liu Anping, IEEE Journal of Solid-State Circuits . 2019,第4期

机译：具有On的12位31.1- $ mu $ W 1-MS / s SAR ADC芯片输入信号独立校准，使用256fF采样电容实现100.4-dB SFDR
2. A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-$mu$m CMOS [J] . Min-Jae Seo, Dong-Hwan Jin, Ye-Dam Kim, IEEE transactions on circuits and systems . I , Regular papers . 2018,第11期

机译：用于生物信号采集的18.5 nW 12位1-kS / s复位节能SAR ADC，采用0.18- $ mu $ m CMOS
3. A 1-$mu$s Ramp Time 12-bit Column-Parallel Flash TDC-Interpolated Single-Slope ADC With Digital Delay-Element Calibration [J] . Deyan Levski, Martin Wäny, Bhaskar Choubey IEEE transactions on circuits and systems . I , Regular papers . 2019,第1期

机译：1- $ mu $ 斜坡时间12位列并行Flash TDC插值具有数字延迟元件校准的单斜率ADC
4. A 12-Bit 31.1UW 1MS/S SAR ADC with On-Chip Input-Signal-Independent Calibration Achieving 100.4DB SFDR Using 256FF Sampling Capacitance [C] . Junhua Shen, Akira Shikata, Anping Liu, IEEE Symposium on VLSI Circuits . 2018

机译：具有片上输入信号独立校准功能的12位31.1UW 1MS / S SAR ADC，使用256FF采样电容实现100.4DB SFDR
5. Physical-Layer Security for Mixed $eta$ – $mu$ and $mathcal {M}$ -Distribution Dual-Hop RF/FSO Systems [O] . Liang Yang, Ting Liu, Jianchao Chen, 2018

机译：混合 $ eta $ - $ mu $ 和 $ mathcal {m} $ - 分配双跳RF / FSO系统

A 12-Bit 31.1- $mu$ W 1-MS/s SAR ADC With On-Chip Input-Signal-Independent Calibration Achieving 100.4-dB SFDR Using 256-fF Sampling Capacitance

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