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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 0.5–1.1-V Adaptive Bypassing SAR ADC Utilizing the Oscillation-Cycle Information of a VCO-Based Comparator
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A 0.5–1.1-V Adaptive Bypassing SAR ADC Utilizing the Oscillation-Cycle Information of a VCO-Based Comparator

机译：利用VCO的比较器的振荡周期信息，0.5-1.1-V自适应旁路SAR ADC

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摘要

A successive approximation register (SAR) analogto-digital converter (ADC) with a voltage-controlled oscillator (VCO)-based comparator is presented in this paper. The relationship between the input voltage and the number of oscillation cycles (NOC) to reach a VCO-comparator decision is explored, implying an inherent coarse quantization in parallel with the normal comparison. The NOC as a design parameter is introduced and analyzed with noise, metastability, and tradeoff considerations. The NOC is exploited to bypass a certain number of SAR cycles for higher power efficiency of VCO-based SAR ADCs. To cope with the process, voltage, and temperature (PVT) variations, an adaptive bypassing technique is proposed, tracking and correcting window sizes in the background. Fabricated in a 40-nm CMOS process, the ADC achieves a peak effective number of bits of 9.71 b at 10 MS/s. Walden figure of merit (FoM) of 2.4-6.85 fJ/conv.-step is obtained over a wide range of supply voltages and sampling rates. Measurement has been carried out under typical, fast-fast, and slow-slow process corners and 0 degrees C-100 degrees C temperature range, showing that the proposed ADC is robust over PVT variations without any off-chip calibration or tuning.
机译：本文介绍了具有电压控制振荡器（VCO）的比较器的连续近似寄存器（SAR）模数转换器（ADC）。探讨了输入电压与振荡周期数（NOC）之间的关系，以达到VCO-比较器决策，暗示与正常比较并行的固有粗量化。作为设计参数的NOC被引入并分析了噪声，衡量性和权衡考虑。利用NOC以绕过一定数量的SAR周期，以获得基于VCO的SAR ADC的更高功率效率。为了应对过程，电压和温度（PVT）变化，提出了一种自适应旁路技术，在背景中跟踪和校正窗口尺寸。在40nm CMOS工艺中制造，ADC在10ms / s下实现9.71b的峰值有效数量。在广泛的电源电压和采样率上获得2.4-6.85 FJ / CONV.-Step的沃尔登人物（FOM）。测量已经在典型，快速快速，缓慢缓慢的过程角落和0摄氏度C-100摄氏度的温度范围内进行，表明所提出的ADC在没有任何异片校准或调谐的情况下对PVT变化具有稳健。

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