A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With −41.3-dB EVM at 1024 QAM in 28-nm CMOS

Markulic Nereo; Renukaswamy Pratap Tumkur; Martens Ewout; van Liempd Barend; Wambacq Piet; Craninckx Jan

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A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With −41.3-dB EVM at 1024 QAM in 28-nm CMOS

机译：5.5GHz背景校准的超自动变送器，具有-41.3-DB EVM，在28-NM CMOS中为1024 QAM

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摘要

We present a subsampling polar transmitter (SSPTX) in 28-nm CMOS that consists of a low-noise phase modulating (PM) digital subsampling phase-locked loop (PLL) and a harmonic rejection mixed (HRM) inverse-class-D (D-1) digital power amplifier (DPA) for amplitude modulation (AM). The DPA is, unlike in a typical polar transmitter (TX), placed within the PLL and the phase-error detection happens directly at the DPA output. The subsampling polar TX thus becomes sensitive not only to phase errors but also to modulation amplitude. That feature enables AM-AM and PM-PM distortion to be detected and cancelled digitally in the background, while the transmitter operates normally. Moreover, the AM-PM cross distortion is filtered by the loop itself. The chip operates from a 0.9-V supply at 5.5 GHz with 2.5 MHz BW (1024 QAM) with average 1.1-dBm output power and total power consumption of 50 mW.

机译：我们在28-nm CMOS中提出了一个超级发射器（SSPTX），其由低噪声相位调制（PM）数字限制阶段锁定环（PLL）和谐波抑制混合（HRM）逆等级-D（D -1）用于幅度调制（AM）的数字功率放大器（DPA）。 DPA与典型的极性发射器（TX）不同，放置在PLL内，相位误差检测直接发生在DPA输出端。如此，极性Tx因此不仅变为相位误差而且还变得敏感，而且变为调制幅度。该特征使得AM-AM和PM-PM失真能够在背景中以数字方式检测并取消，而发射机正常运行。此外，通过环本身滤除AM-PM交叉失真。该芯片以5.5 GHz的0.9-V电源，具有2.5 MHz BW（1024 QAM），平均1.1-DBM输出功率和50 MW的总功耗。

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来源
《IEEE Journal of Solid-State Circuits》 |2019年第4期|1059-1073|共15页
作者
Markulic Nereo; Renukaswamy Pratap Tumkur; Martens Ewout; van Liempd Barend; Wambacq Piet; Craninckx Jan;
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作者单位

IMEC Leuven Belgium;

IMEC Leuven Belgium|Vrije Univ Brussel Dept ETRO Brussels Belgium;

IMEC Leuven Belgium;

IMEC Leuven Belgium;

Vrije Univ Brussel Dept ETRO Brussels Belgium;

IMEC Leuven Belgium;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类
关键词
Background calibration; digital-to-time converter (DTC); linearization; phase-locked loop (PLL); polar transmitter; subsampling; transmitter;

机译：背景校准;数字到时转换器（DTC）;线性化;锁相环（PLL）;极发射器;分支;发射机;

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专利

1. A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With −41.3-dB EVM at 1024 QAM in 28-nm CMOS [J] . Markulic Nereo, Renukaswamy Pratap Tumkur, Martens Ewout, IEEE Journal of Solid-State Circuits . 2019,第4期

机译：在28nm CMOS中具有1024 QAM且−41.3 dB EVM的5.5 GHz背景校准的二次采样极性发送器
2. 1024-QAM High Image Rejection $E$-Band Sub-Harmonic IQ Modulator and Transmitter in 65-nm CMOS Process [J] . Lin W.-H., Yang H.-Y., Tsai J.-H., IEEE Transactions on Microwave Theory and Techniques . 2013,第11期

机译：采用65 nm CMOS工艺的1024 QAM高图像抑制$ E $波段亚谐波IQ调制器和发送器
3. A 43.6-dB SNDR 1-GS/s 3.2-mW SAR ADC With Background-Calibrated Fine and Coarse Comparators in 28-nm CMOS [J] . Guanhua Wang, Kexu Sun, Qing Zhang, IEEE transactions on very large scale integration (VLSI) systems . 2019,第9期

机译：具有背景校准的精细和粗糙比较器的43.6dB SNDR 1-GS / s 3.2mW SAR ADC，采用28nm CMOS
4. A 5.5 GHz Background-Calibrated Subsampling Polar Transmitter with −41.3 DB EVM at 1024 OAM in 28NM CMOS [C] . Nereo Markulic, Pratap Renukaswarny, Ewout Martens, IEEE Symposium on VLSI Circuits . 2018

机译：5.5 GHz背景校准的二次采样极性发送器，在28NM CMOS下具有1024 OAM的−41.3 DB EVM
5. Ultra-wideband mm-Wave I/Q CMOS Transmitters for High-order QAM Waveforms [D] . Al-Rubaye, Hasan. 2018

机译：超宽带MM波I / Q CMOS发射器，用于高阶QAM波形
6. A 67-86 GHz Spectrum-Efficient CMOS Transmitter Supporting 1024-QAM With a Process-Variation-Tolerant Design [O] . Wen-Jie Lin, Jeng-Han Tsai, Jen-Hao Cheng, 2020

机译：一个67-86 GHz频谱 - 高效的CMOS发射器，配有一个1024-QAM，具有处理变化容差设计

A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With −41.3-dB EVM at 1024 QAM in 28-nm CMOS

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