A 290-mV, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell

Sinangil Mahmut E.; Lin Yen-Ting; Liao Hung-Jen; Chang Jonathan

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A 290-mV, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell

机译：使用12T写入争用和读自由位竞争的290 mV，7-NM超低电压单端口SRAM编译器设计

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摘要

In this paper, we present an ultra-low voltage one-port static random access memory (SRAM) compiler targeting small to medium array sizes to provide a smaller area solution compared to conventional 6T-based SRAMs. A 12T write contention and read upset free bit-cell are used in the design. Array architecture employs a read-modify-write scheme to support bit-write (BW) masking and column multiplexing. Built-in-self-test (BIST) and synchronous write-through (SWT) options are also supported to provide testability features, while power management (PM) option is included to provide low-leakage sleep and shut-down modes. The proposed design is fabricated in 7-nm FinFET technology and achieves the lowest reported V-min of 290 mV in this technology.

机译：在本文中，我们介绍了一个超低电压单端口静态随机存取存储器（SRAM）编译器，其针对中等阵列尺寸，与传统的6T基SRAM相比提供较小的区域解决方案。在设计中使用12T写入争用和读入心自由位单元。数组架构采用读取修改写入方案来支持位写（BW）屏蔽和列复用。还支持内置自检（BIST）和同步写入（SWT）选项以提供可测试性功能，而电源管理（PM）选项包含在内以提供低泄漏睡眠和关闭模式。拟议的设计是在7-NM FinFET技术中制造的，在这项技术中实现了最低报告的V-Min V-min。

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来源
《IEEE Journal of Solid-State Circuits》 |2019年第4期|1152-1160|共9页
作者
Sinangil Mahmut E.; Lin Yen-Ting; Liao Hung-Jen; Chang Jonathan;
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作者单位

Taiwan Semicond Mfg Co San Jose CA 95134 USA;

Taiwan Semicond Mfg Co San Jose CA 95134 USA;

Taiwan Semicond Mfg Co Hsinchu 30078 Taiwan;

Taiwan Semicond Mfg Co Hsinchu 30078 Taiwan;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类
关键词
12T bit-cell; low-voltage static random access memory (SRAM); SRAM compiler;

机译：12T位细胞;低压静态随机存取存储器（SRAM）;SRAM编译器;

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专利

1. A 290-mV, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell [J] . Sinangil Mahmut E., Lin Yen-Ting, Liao Hung-Jen, IEEE Journal of Solid-State Circuits . 2019,第4期

机译：290mV，7nm超低电压单端口SRAM编译器设计，使用12T写入争用和读取翻转自由位单元
2. Quadruple Cross-Coupled Latch-Based 10T and 12T SRAM Bit-Cell Designs for Highly Reliable Terrestrial Applications [J] . Jiang Jianwei, Xu Yiran, Zhu Wenyi, IEEE transactions on circuits and systems . I , Regular papers . 2019,第3期

机译：基于四路交叉耦合，基于锁存器的10T和12T SRAM位单元设计，用于高度可靠的地面应用
3. A 32 nm Read Disturb-free 11T SRAM Cell with Improved Write Ability* [J] . Mansore S. R., Gamad R. S., Mishra D. K. Journal of circuits, systems and computers . 2020,第5期

机译：32 nm读取无干扰的11T SRAM单元，具有改进的写入能力*
4. A 290MV Ultra-Low Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell in 7NM FinFET Technology [C] . Mahmut E. Sinangil, Yen-Ting Lin, H. J. Liao, IEEE Symposium on VLSI Circuits . 2018

机译：290MV超低电压单端口SRAM编译器设计，采用7NM FinFET技术中的12T写入争用和读取翻转自由位单元
5. OSUSPRAM: Design of a single port SRAM compiler in NCSU FreePDK45 process. [D] . Sundararajan, Gopalakrishnan. 2010

机译：OSUSPRAM：在NCSU FreePDK45流程中设计单端口SRAM编译器。
6. A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing [O] . Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, 2012

机译：具有交叉点数据感知写字线结构，负位线和自适应读取操作时序跟踪的单端无干扰9T亚阈值SRAM

A 290-mV, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell

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