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首页> 外文期刊>IEEE Journal of Solid-State Circuits >An Analog-Proportional Digital-Integral Multiloop Digital LDO With PSR Improvement and LCO Reduction
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An Analog-Proportional Digital-Integral Multiloop Digital LDO With PSR Improvement and LCO Reduction

机译：具有PSR改进和LCO减少的模拟成比例的数字整体多环数码LDO

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摘要

This article presents a low-dropout regulator (LDO), with analog-proportional (AP) and digital integral (DI) controls. The design concerns are discussed at first, on how to improve the load transient response, enhance the power supply rejection (PSR), and reduce the limit cycle oscillation (LCO). For a good output dc accuracy, the DI section is implemented with shift-register-based coarse- and fine-tuning loops. Meanwhile, the AP section, based on a low-supply flipped-voltage follower (FVF), can respond fast to the load step and input supply ripple. A replica loop is used to define the steady-state output current of AP, allowing a sufficient dynamic swing against the supply ripple. To lower the load current range with no LCO, the AP section will output all the current at very light load. An error amplifier (EA) with moderate gain is added to improve the light-load output accuracy. This EA also improves the PSR by approximately 6 dB. Fabricated in a 65-nm CMOS process, a 65-mV undershoot is measured with a 0-10-mA load current step under 0.6-V supply voltage and 50-mV dropout. Due to the fast AP, a 5-MHz operation clock is applied to the digital section, reducing the overall quiescent current to 29 mu A. A 0.37-ps figure of merit (FoM) is then achieved. A -22-dB PSR at 1 MHz is measured at 0.6-V supply, 100-mV dropout, and 10-mA load current.
机译：本文介绍了一个低丢失的调节器（LDO），模拟比例（AP）和数字积分（DI）控件。首先讨论了设计顾虑，关于如何提高负载瞬态响应，增强电源抑制（PSR），并减少极限循环振荡（LCO）。为了良好的输出直流精度，DI部分用基于移位寄存器的粗大和微调环路实现。同时，基于低电源翻转电压跟随器（FVF）的AP部分可以快速响应负载步骤和输入电源纹波。复制循环用于定义AP的稳态输出电流，允许对电源纹波进行足够的动态摆动。为了降低没有LCO的负载电流范围，AP部分将在非常轻的负载下输出所有电流。添加了适度增益的误差放大器（EA）以提高光负荷输出精度。该EA还将PSR改进约6dB。在65纳米CMOS工艺中制造，使用0-10mA的负载电流步骤测量65mV的下冲，在0.6V电源电压下和50mV丢失。由于快速AP，将5-MHz操作时钟施加到数字截面，将整体静态电流降低到29μmA.然后实现了0.37ps的优点（FOM）的优点图。在1 MHz的A-22-DB PSR以0.6V供电，100mM辍学和10 mA载荷电流测量。

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  • 来源
    《IEEE Journal of Solid-State Circuits》 |2020年第6期|1637-1650|共14页
  • 作者

    Huang Mo; Lu Yan; Martins Rui P.;

  • 作者单位

    Univ Macau State Key Lab Analog & Mixed Signal VLSI Inst Microelect Macau 999078 Peoples R China|Univ Macau Fac Sci & Technol Dept Elect & Comp Engn Macau 999078 Peoples R China|South China Univ Technol Sch Elect & Informat Engn Guangzhou 510641 Guangdong Peoples R China;

    Univ Macau State Key Lab Analog & Mixed Signal VLSI Inst Microelect Macau 999078 Peoples R China|Univ Macau Fac Sci & Technol Dept Elect & Comp Engn Macau 999078 Peoples R China;

    Univ Macau State Key Lab Analog & Mixed Signal VLSI Inst Microelect Macau 999078 Peoples R China|Univ Macau Fac Sci & Technol Dept Elect & Comp Engn Macau 999078 Peoples R China;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Digital; fast response; low dropout regulator (LDO); power supply rejection (PSR); proportional-integral (PI) control;

    机译：数字;快速响应;低压丢弃调节器（LDO）;电源抑制（PSR）;比例积分（PI）控制;

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