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首页> 外文期刊>IEEE Journal of Solid-State Circuits >C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism
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C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism

机译：C3SRAM：基于鲁棒电容耦合计算机制的内存计算SRAM宏

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This article presents C3SRAM, an in-memory-computing SRAM macro. The macro is an SRAM module with the circuits embedded in bitcells and peripherals to perform hardware acceleration for neural networks with binarized weights and activations. The macro utilizes analog-mixed-signal (AMS) capacitive-coupling computing to evaluate the main computations of binary neural networks, binary-multiply-and-accumulate operations. Without the need to access the stored weights by individual row, the macro asserts all its rows simultaneously and forms an analog voltage at the read bitline node through capacitive voltage division. With one analog-to-digital converter (ADC) per column, the macro realizes fully parallel vector-matrix multiplication in a single cycle. The network type that the macro supports and the computing mechanism it utilizes are determined by the robustness and error tolerance necessary in AMS computing. The C3SRAM macro is prototyped in a 65-nm CMOS. It demonstrates an energy efficiency of 672 TOPS/W and a speed of 1638 GOPS (20.2 TOPS/mm(2)), achieving 3975x better energy-delay product than the conventional digital baseline performing the same operation. The macro achieves 98.3% accuracy for MNIST and 85.5% for CIFAR-10, which is among the best in-memory computing works in terms of energy efficiency and inference accuracy tradeoff.
机译：本文提出了C3SRAM，一个内存计算的SRAM宏。宏是一个SRAM模块，具有嵌入位单元和外设中的电路，以对具有二值化权重和激活的神经网络执行硬件加速。宏利用模拟混合信号（AMS）电容耦合计算来评估二进制神经网络的主要计算，二进制 - 乘法和累积操作。无需通过单个行访问存储的权重，宏同时断言所有行，并通过电容电压划分在读取位线节点处形成模拟电压。通过每列的一个模数转换器（ADC），宏在单个周期中实现完全并行矢量矩阵乘法。它利用的宏支持和计算机制的网络类型由AMS计算所需的鲁棒性和误差公差决定。 C3SRAM宏在65nm CMOS中原型。它展示了672个顶部/倍的能量效率和1638个磁气的速度（20.2顶部/ mm（2）），比传统的数字基线执行相同的操作，实现3975倍的能量延迟产品。宏可实现98.3％的MNIST精度和CIFAR-10的85.5％，这是能源效率和推理准确性权衡的最佳内存计算工作之一。

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