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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 20.5 TOPS Multicore SoC With DNN Accelerator and Image Signal Processor for Automotive Applications
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A 20.5 TOPS Multicore SoC With DNN Accelerator and Image Signal Processor for Automotive Applications

机译：使用DNN加速器和用于汽车应用的DNN加速器和图像信号处理器的20.5个顶部MultiCore SoC

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摘要

Advanced driver-assistance systems (ADASs) that provide machine support to avoid critical accidents are already in wide use in vehicles in today's market. SoCs for such systems have several requirements: 1) high computational performance to run several advanced algorithms at low latency; 2) low power consumption to permit running under the extreme heat and power conditions of real-world vehicles; and 3) high reliability to reduce the risk of serious accidents caused by faults. This article presents a novel SoC for ADAS applications, which resolves these difficult challenges. To achieve high performance with low power consumption, the SoC adopts the heterogeneous architecture, with ten processors, four DSPs, and eight types of accelerators, including the DNN accelerator and the image signal processor (ISP). To achieve higher reliability, the SoC implements several safety mechanisms, including system partitioning to prevent fault propagation, diagnostic features to detect faults, and a dedicated controller to operate runtime built-in self-test (BIST) of the ISP's diagnostic features during the vertical blanking interval (VBLANK). The SoC is implemented in a 16-nm process, and its size is 94.52 mm(2). Peak performance of 20.5 TOPS and low power consumption of 9.78 W are achieved.
机译：高级驾驶员辅助系统（ADASS）为避免批判性事故提供机器支持，已经在当今市场中的车辆广泛使用。这些系统的SOC具有多种要求：1）在低延迟下运行几种高级算法的高计算性能; 2）低功耗允许在现实世界车辆的极端热量和电源条件下运行; 3）高可靠性，以降低故障引起的严重事故的风险。本文为ADAS应用提供了一部小型SOC，解决了这些困难的挑战。为了实现低功耗的高性能，SOC采用异质架构，具有十个处理器，四种DSP和8种类型的加速器，包括DNN加速器和图像信号处理器（ISP）。为了实现更高的可靠性，SOC实现了多种安全机制，包括系统分区，以防止故障传播，检测故障的诊断功能以及专用控制器，以在垂直期间运行ISP诊断功能的运行时内置自检（BIST）消隐间隔（VBLANK）。 SOC在16纳米工艺中实现，其尺寸为94.52mm（2）。实现了20.5个顶部和低功耗为9.78W的峰值性能。

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