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首页> 外文期刊>IEEE Journal of Solid-State Circuits >Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14-nm SOI CMOS
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Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14-nm SOI CMOS

机译：LDO微观调用仪的分布式网络为14-NM SOI CMOS提供了24核微处理器的亚微粒电流DVF和IR滴补偿

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摘要

A distributed network of low-dropout (LDO) microregulators (uREGs) senses and corrects the voltages at multiple points on a power supply grid in a multi-core microprocessor to reduce errors due to IR drops. A voltage regulator controller (VREGC) compares the voltages at various points on the grid to a programmable reference and delivers a set of corrective 2-b up/down (UP/DN) codes (global feedback) to the distributed uREGs across the core. Inside each uREG, the UP/DN codes control a local charge pump that sets the reference for an asynchronous comparator that turns on and off a pMOS passgate with a sub-nanosecond response. To mitigate the self-generated ripple, hybrid fast/slow passgate control is employed, whereby a parallel pMOS passgate with a slew-rate-limited gate drive is used to supply the dc portion of the load current. The distributed regulator architecture includes a scheme for limiting the degree of load-sharing imbalances among its uREGs due to the VREGC comparator offsets. Adding a switched-capacitor (SC) accelerator to the charge pump of each uREG speeds up the output-voltage transitions by up to 17 $imes $ for greater dynamic voltage and frequency scaling (DVFS) savings. Line and load regulations are 9 mV/V and 1.1 mV/A, respectively. The regulator achieves a peak power efficiency of 95.2% and a peak current efficiency of 99.1%. It reaches a peak power density of 82.3 W/mm(2).
机译：低压丢失（LDO）微电路（UREG）的分布式网络感测并校正多核微处理器中电源网格上的多个点处的电压，以减少由于IR滴引起的误差。电压调节器控制器（VREGC）将网格上的各个点处的电压与可编程参考进行比较，并将一组校正的2-B向上/向下（向上/ DN）代码（全局反馈）（全局反馈）传送到核心的分布式UREG。在每个UREG中，UP / DN码控制局部电荷泵，该泵为异步比较器设置参考，该比较器与子纳秒响应打开和关闭PMOS频率。为了减轻自生成的纹波，采用混合快速/慢速频率控制，由此使用具有弹簧速率限制栅极驱动器的并联PMOS频率来提供负载电流的DC部分。分布式调节器架构包括由于VREGC比较器偏移而限制其UREG之间的负载共享不平衡程度的方案。向每个UREG的电荷泵添加开关电容（SC）加速器将输出电压转换加速多达17美元 Times $以获得更高的动态电压和频率缩放（DVFS）节省。线路和载荷规定分别为9 mV / v和1.1 mV / a。该调节器达到95.2％的峰值功率效率，峰值电流效率为99.1％。它达到82.3W / mm（2）的峰值功率密度。

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